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1995 data sheet m pd78c17, 78c18 the information in this document is subject to change without notice. the mark h shows revised points. document no. ic-2789b (o.d.no. ic-8048b) date published june 1995 p printed in japan 8-bit single-chip microcontroller (with a/d converter) the m pd78c18 is an 8-bit cmos microcontroller which integrates 16-bit alu, rom, ram, an a/d converter, a multi-function timer/event counter, and a general-purpose serial interface onto a single chip, and whose memory (rom/ram) is externally expandable up to 31 kbytes. the m pd78c18 can operate at low power consumption because of its cmos architecure and is provided with a standby function that enables data retention with an even lower power consumption. the m pd78c17 is the rom-less version of the m pd78c18. its memory (rom/ram) is expandable externally up to 63 kbytes. a detailed explanation of the functions is provided in the user's manual listed below. it should be read before starting design work. 87ad series m pd78c18 user's manual: ieu-1314 features ? 159 types of instructions: 87ad series instruction set plus multiply/divide and 16-bit operation instructions ? instruction cycle: 0.8 m s (at 15-mhz operation) ? internal rom: 32768 x 8 bits ( m pd78c18 only) ? internal ram: 1024 x 8 bits ? up to 64 kbytes of memory (rom/ram) can be directly addressed. ? high-resolution 8-bit a/d converter: 8 analog inputs ? general-purpose serial interface: asynchronous, synchronous, i/o interface modes ? multi-function 16-bit timer/event counter ? two 8-bit timers ? i/o lines input/output ports : 28 ( m pd78c17), 40 ( m pd78c18) edge detection inputs : 4 ? 11 interrupt functions external : 3, internal: 8 (non-maskable: 1, maskable: 10) ? zero-cross detection function: (2 inputs) ? standby function: halt mode, hardware/software stop mode ? mask option pull-up resistors can be incorporated into ports a, b, and c. ( m pd78c18 only) ordering information part number package m pd78c17cw 64-pin plastic shrink dip (750 mils) m pd78c17gf-3be 64-pin plastic qfp (14 x 20 mm) m pd78c17gq-36 64-pin plastic quip m pd78c18cw-xxx 64-pin plastic shrink dip (750 mils) m pd78c18gf-xxx-3be 64-pin plastic qfp (14 x 20 mm) m pd78c18gq-xxx-36 64-pin plastic quip 1990 mos integrated circuit
2 m pd78c17,78c18 1 pa0 2 pa1 3 pa2 4 pa3 5 pa4 6 pa5 7 pa6 8 pa7 9 pb0 10 pb1 11 pb2 12 pb3 13 pb4 14 pb5 15 pb6 16 pb7 17 pc0/t x d 18 pc1/r x d 19 pc2/sck 20 pc3/int2 21 pc4/to 22 pc5/ci 23 pc6/co0 24 pc7/co1 25 nmi 26 int1 27 mode1 28 reset 29 mode0 30 x2 31 x1 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v dd stop pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd av aref an7 an6 an5 an4 an3 an2 an1 an0 av ss pin configuration (top view) m m m pd78c17cw, m pd78c17gq-36 m pd78c18cw-xxx, m pd78c18gq-xxx-36
3 m pd78c17,78c18 an4 an3 an2 an1 an0 av ss v ss x1 x2 mode0 reset mode1 int1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 pa0 pa1 pd3 pd4 pd5 pd6 pd7 stop v dd pa2 pa3 pa4 pa5 45678910111213141516171819 pf3 pf2 pf1 pf0 ale wr rd av dd v aref an7 an6 an5 pf7 pf6 pf5 pf4 51 50 49 123 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/t x d pc1/r x d pc2/sck pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 nmi pa6 pa7 pb0 pd2 pd1 pd0 m pd78c17gf-3be m pd78c18gf-xxx-3be
4 m pd78c17,78c18 serial i/o x1 alu (8/16) pc0/t x d x2 pc1/r x d pc2/sck osc int. control nmi int1 8 8 4 8 timer timer/event counter 8 8 8 pc3/int2/ti pc4/to pc5/ci pc6/co0 pc7/co1 a/d converter v aref av dd av ss 8 latch inc/dec pc sp ea ea' va bc de hl v' a' b' c' d' e' h' l' buffer 10 16 15 program note 1 memory (32-kbyte) data note 4 memory (1-kbyte) 8/16 inst.reg latch latch 16 16 internal data bus 16 16 16 6 inst. decoder 8 8 stand by control system control read/write control reset v ss v dd stop mode0 mode1 ale wr rd port f 8 8 8 port d 8 8 8 port c 8 pc7-0 note 3 8 port b 8 pb7-0 note 3 8 port a 8 pa7-0 note 3 8 16 an7-0 psw pd7-0/ ad7-0 note 2 pf7-0/ ab15-8 note 2 main g.r alt g.r block diagram notes 1. program memory is not incorporated in the m pd78c17. 2. pf3 to pf0 and pd7 to pd0 are operated only as ab11 to ab8 and ad7 to ad0 in the m pd78c17. 3. pull-up resistor can be incorporated by the mask option in the m pd78c18. 4. can be used only when rae bit of mm register is 1. when it is 0, an external memory is necessary.
5 m pd78c17,78c18 contents 1. pin functions ............................................................................................................................... ........... 7 1.1 list of pin function ............................................................................................................................... .......7 1.2 pin input/output circuits ..........................................................................................................................9 1.3 pin mask options ............................................................................................................................... ..........15 1.4 unused pin connections ..........................................................................................................................15 2. internal block functions ..............................................................................................................16 2.1 registers ............................................................................................................................... ..........................16 2.2 arithmetic logic unit (alu) .....................................................................................................................17 2.3 program status word (psw) ..................................................................................................................17 2.4 memory ............................................................................................................................... .............................19 2.5 port functions ............................................................................................................................... ..............22 2.6 timer ............................................................................................................................... ...................................31 2.7 timer/event counter ............................................................................................................................... ..34 2.8 serial interface ............................................................................................................................... ............41 2.9 analog/digital converter ......................................................................................................................52 2.10 zero-cross detector ............................................................................................................................... ..55 3. interrupt functions .........................................................................................................................57 3.1 interrupt control circuit configuration ......................................................................................58 3.2 non-maskable interrupt operation ...................................................................................................61 3.3 maskable interrupt operation ............................................................................................................63 3.4 interrupt operation by softi instruction ......................................................................................64 4. standby functions ............................................................................................................................65 4.1 halt mode ............................................................................................................................... ........................65 4.2 halt mode release ............................................................................................................................... .......66 4.3 software stop mode ............................................................................................................................... ..68 4.4 software stop mode release ................................................................................................................68 4.5 hardware stop mode ............................................................................................................................... ..69 4.6 hardware stop mode release ...............................................................................................................70 4.7 low supply voltage data retention mode ..................................................................................... 71 5. reset operations ............................................................................................................................... .72 6. instruction set ............................................................................................................................... ....73 6.1 identifier/description of operand ......................................................................................................73 6.2 symbol description of instruction code ........................................................................................74 6.3 instruction execution time ...................................................................................................................75 7. list of mode registers .....................................................................................................................87 8. electrical specifications ................................................................................................................88 9. characteristic curves .....................................................................................................................99 10. package drawings ...........................................................................................................................102
6 m pd78c17,78c18 11. recommended soldering conditions ......................................................................................105 12. differences among m pd78c18, m pd78c14, and m pd78c12a ....................................................106 appendix. development tools ..........................................................................................................107
7 m pd78c17,78c18 1. pin functions 1.1 list of pin function (1/2) function pin name i/o pa7 to pa0 (port a) input-output 8-bit input-output port, which can specify input/output (port a) bit-wise. 8-bit input-output port, which can specify input/output (port b) bit-wise. pb7 to pb0 (port b) input-output port c 8-bit input-output port, which can specify input/output bit-wise. pc1/rxd receive data input pin for serial data. input-output/ input pc0/t x d input-output/ output transmit data output pin for serial data. serial clock input-output pin for serial clock. it becomes output pin for the internal clock use, and input pin for the external. pc2/sck interrupt request/timer input maskable interrupt input pin of the edge trigger (falling edge), or an external clock input pin for a timer. also, it can be used as a zero-cross detection pin for ac input. input-output/ input/input pc3/int2/ti pc4/to timer output square wave defining one cycle of internal clock or timer counter time as half cycle is output. input-output/ output input-output/ input pc5/ci counter input external pulse input pin to timer/event counter. pc6/co0 pc7/co1 counter output 0, 1 programmable square wave output by timer/event counter. input-output/ output pd7 to pd0/ ad7 to ad0 input-output/ input-output address/data bus when external memory is used, it becomes multiplexed address/data bus. port d 8-bit input-output port, which can specify input/output in byte units ( m pd78c18). pf7 to pf0/ ab15 to ab8 input-output/ output port f 8-bit input-output port, which can specify input/output bit-wise. address bus when external memory is used, it becomes address bus. output strobe signal which is output for write operation of external memory. it becomes high in any cycle other than the data write machine cycle of external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high- impedance. wr (write strobe) output rd (read strobe) output ale (address latch enable) strobe signal which is output for read operation of external memory. it becomes high in any cycle other than the read machine cycle of external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high-impedance. strobe signal to latch externally the lower address information which is output to pd7 to pd0 pins to access external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high-impedance. input-output/ input-output
8 m pd78c17,78c18 x1, x2 (crystal) reset (reset) stop (stop) v dd v ss 1.1 list of pin function (2/2) function pin name i/o input-output the m pd78c18 sets mode0 pin to 0 (low level), and mode1 pin to 1 (high level). note the m pd78c17 allows you to set mode0, mode1 pins to select 4 k, 16 k, or 63 kbytes for the size of the memory which is installed externally. mode0 mode1 external memory 0 0 4 kbytes 1 0 16 kbytes 1 1 63 kbytes also, when each of mode0 and mode1 pins is set to 1 note , it is synchronized to ale to output a control signal. non-maskable interrupt input pin of the edge trigger (falling edge) a maskable interrupt input pin of the edge trigger (rising edge). also, it can be used as a zero-cross detection pin for ac input. 8 pins of analog input to a/d converter. an7 to an4 can be used as edge detection (falling edge) input. a common pin serving both as a reference voltage input pin for a/d converter and as a control pin for a/d converter operation. power supply pin for a/d converter. gnd pin for a/d converter. crystal connection pins for system clock oscillation. x1 should be input when a clock is supplied from outside. inverted clock of x1 should be input to x2. low-level active system reset input. control signal input pin in hardware stop mode. the oscillation stops when the low- level is input. positive power supply pin. gnd pin. mode0 mode1 (mode) nmi (non-maskable interrupt) input int1 (interrupt request) an7 to an0 (analog input) input input input v aref (reference voltage) av dd (analog v dd ) av ss (analog v ss ) input input note connect a pull-up resistor. resistance r should be 4 [k w ] r 0.4t cyc [k w ] (t cyc is in nanoseconds). remark the m pd78c18 can incorporate (mask option) pull-up resistors on to ports a, b, and c.
9 m pd78c17,78c18 pa7 to pa0 5-a reset 2 pb7 to pb0 5-a rd 4 pc1 and pc0 5-a wr 4 pc2/sck 8-a ale 4 pc3/int2 10-a stop 2 pc7 to pc4 5-a mode0 11 pd7 to pd0 5 mode1 11 pf7 to pf0 5 an3 to an0 7 nmi 2 an7 to an4 12 int1 9 v aref 13 pa7 to pa0 5 reset 2 pb7 to pb0 5 rd 4 pc1 and pc0 5 wr 4 pc2/sck 8 ale 4 pc3/int2 10 stop 2 pc7 to pc4 5 mode0 11 ad7 to ad0 5 mode1 11 ab11 to ab8 5 an3 to an0 7 pf7 to pf4 5 an7 to an4 12 nmi 2 v aref 13 int1 9 pin name pin name type no. type no. 1.2 pin input/output circuits table 1-1 and 1-2, and figures (1) to (15) show input/output circuits of each pin in a schematic form. table 1-1 pin type no. for m pd78c17 table 1-2 pin type no. for m pd78c18 pin name pin name type no. type no.
10 m pd78c17,78c18 p-ch output disable n-ch out v dd output data v p-ch output disable n-ch out dd output data v dd p- in n- ch ch in (1) type 1 (2) type 2 (3) type 4 (4) type 4-a
11 m pd78c17,78c18 p-ch n-ch av dd av dd av ss sampling c + reference voltage (from voltage tap of serial resistance string) in (5) type 5 (6) type 5-a (7) type 7 (8) type 8 in/out output data output disable type 4 type 1 in/out output data output disable type 4-a type 1 type 5 type 2 output data output disable in/out mcc n-ch n-ch
12 m pd78c17,78c18 (9) type 8-a (10) type 9 (11) type 10 type 2 in self bias enable data type 5-a type 2 output data output disable in/out mcc n-ch n-ch type 5 type 9 output data output disable in/out mcc self bias enable n-ch n-ch
13 m pd78c17,78c18 (12) type 10-a (13) type 11 (14) type 12 type 1 n-ch output data in/out in type 7 type 2 edge detector type 5-a type 9 output data output disable in/out mcc self bias enable n-ch n-ch
14 m pd78c17,78c18 type 1 in av ss stop mode p-ch (15) type 13
15 m pd78c17,78c18 1.3 pin mask options the m pd78c18 has the following mask options, which can be selected bit-wise according to the application. pin name mask options pa7 to pa0 pb7 to pb0 pc7 to pc0 pd7 to pd0 pf7 to pf0 rd wr ale stop int1, nmi av dd av aref av ss an7 to an0 recommended connection pin connect to v dd connect to v ss or v dd connect to v dd connect to v ss connect to av ss or av dd leave open connect to v ss or v dd via a resistor cautions 1. zero-cross detection function will not operate properly if pull-up resistor is incorporated in pc3. 2. the m pd78c17 has no mask option. 1.4 unused pin connections pa7 to pa0 pb7 to pb0 pc7 to pc0 pull-up resistor can be incorporated h
16 m pd78c17,78c18 2. internal block functions 2.1 registers the central registers are the sixteen 8-bit registers and four 16-bit registers shown in fig. 2-1. fig. 2-1 register configuration (a) general registers (b, c, d, e, h, l) there are two sets of general registers (main: b, c, d, e, h, l; alt: b, c, d, e, h, l). they function as auxiliary registers for the accumulator, and have a data pointer function as register pairs (bc, de, hl; bc, de, hl). in particular, four register pairs de, de, hl, and hl, have a base register function. when the two sets are used, if an interrupt occurs in one set, the register contents are saved into the other register set without saving them into the memory so that interrupt servicing can be carried out. the other set of registers can also be used as data pointer expansion registers. two addressing modes, single- step automatic increment/decrement modes and a two-step automatic increment mode, are available for the register pairs, de, hl, de, and hl, so that the processing time can be reduced. bc, de, and hl can be simultaneously replaced with the alt register by means of the exx instruction. the hl register can be independently replaced with the alt register by means of the exh instruction. (b) working register vector register (v) when a working area is set in the memory space, the high-order 8 bits of the memory address are selected using the v register and the low-order 8 bits are addressed by the immediate data in the instruc- tion. thus, the memory area specified with the v register can be used as working registers with a 256 x 8- bit configuration. because a working register can be specified with a 1-byte address field, program reduction is possible by using the working area for software flags, parameters, and counters. the v register can be replaced with the alt register paired with an accumulator by means of the exa instruction. pc sp 15 15 0 0 0 ea 07 7 v b d h a c e l 15 0 0 ea' 07 7 v' b' d' h' a' c' e' l' main alt
17 m pd78c17,78c18 (c) accumulator (a) in the m pd78c17 and 78c18, because an accumulator type architecture is used, 8-bit data processing such as 8-bit arithmetic and logical operation instructions is mainly performed by this accumulator. this accumulator can be replaced with the alt register paired with the vector register (v) by means of the exa instruction. (d) expansion accumulator (ea) 16-bit data processing such as 16-bit arithmetic and logical operation instructions is mainly performed by ea. this accumulator can be replaced with the alt register ea by means of the exa instruction. (e) program counter (pc) this is a 16-bit register which holds information on the next program address to be executed. this register is normally incremented automatically according to the number of bytes of the instruction to be fetched. when an instruction associated with a branch is executed, immediate data or register contents are loaded. reset input clears this counter to 0000h. (f) stack pointer (sp) this is a 16-bit register which holds the start address of the memory stack area (lifo format). sp contents are decremented when a call or push instruction is executed or an interrupt is generated, and incremented when a return or pop instruction is executed. 2.2 arithmetic logic unit (alu) ...16 bits the alu executes data processing such as 8-bit arithmetic and logical operations, shift and rotation, data processing such as 16-bit arithmetic and logical operations and shift operations, 8-bit multiplication and 16-bit by 8-bit division. 2.3 program status word (psw) this word consists of 6 types of flags which are set/reset according to instruction execution results. three of these flags (z, hc, and cy) can be tested by an instruction. psw contents are automatically saved to the stack when an interrupt (external, internal, or softi instruction) is generated, and restored by the reti instruction. reset input resets all bits to (0). fig. 2-2 psw configuration (a) z (zero) when the operation result is zero, this flag is set (1). in all other cases, it is reset (0). (b) sk (skip) when the skip condition is satisfied, this flag is set (1). if the condition is not satisfied, it is reset (0). (c) hc (half carry) if an 8-bit operation generates a carry out of bit 3 or a borrow into bit 3, this flag is set (1). in all other cases, it is reset (0). (d) l1 when the mvi a, byte instruction is stacked, this flag is set (1). in all other cases, it is reset (0). 76543 210 0 z sk hc l1 l0 0 cy
18 m pd78c17,78c18 (e) l0 when the mvi l, byte;lxi h, word instruction is stacked, this flag is set (1). in all other cases, it is reset (0). (f) cy (carry) when a 16-bit operation generates a carry out of or a borrow into bit 7 or 15, this flag is set (1). in all other cases, it is reset (0). when one of 35 types of alu instructions, rotation instructions, or carry manipulation instructions is executed, various flags are affected as shown in table 2-1. table 2-1 flag operations addx adcx subx sbbx anax orax xrax addncx subnbx gtax ltax onax offax neax eqax adi aci sui sbi ani ori xri adinc suinb gti lti oni offi nei eqi immediate reg, memory operation skip d3 l1 d6 z d5 sk d4 hc d2 l0 d0 cy ? rlr rll slr sll drlr drll dslr dsll slrc sllc stc clc mvi a, byte mvi l, byte lxi h, word bit sk skn skit skn it rets other all instructions 0 ? 0 0 ? ? 0 0 0 l l ? ? 0 0 ? ? ? ? 0 0 l l ? ? 0 0 ? ? ? 0 0 l ? 0 ? 0 0 ? 0 0 l l ? 0 l 0 ? 0 0 l l 1 0 0 l l 0 1 0 l ll l l 0 1 l 0 0 l l 0 l l l 1 00 l l l 0 0 0 l ........ affected (set or reset) 1 ........ set 0 ........ reset ........ no? affected ? l ? ? aniw oriw gtiw ltiw oniw offiw neiw eqiw addw adcw subw sbbw anaw oraw xraw addncw subnbw gtaw ltaw onaw offaw neaw eqaw inrw dcrw add adc sub sbb dadd dadc dsub dsbb eadd esub ana ora xra dan dor dxr addnc subnb gta lta daddnc dsubnb dgt dlt ona offa don doff nea eqa dne deq inr dcr daa ? ? 0 0 0 0 l
19 m pd78c17,78c18 2.4 memory the m pd78c17 and 78c18 can address a maximum of 64 kbytes of memory. the memory maps are shown in figs. 2-3 and 2-4. the external memory area and the internal ram area can be freely used as program memory and data memory. because the access timing for internal memory and external memory are the same, pro- cessing can be executed at high speeds. (a) interrupt start addresses the interrupt start addresses are all fixed as follows: nmi ....................... 0004h intt0/intt1 ......... 0008h int1/int2 ............. 0010h inte0/inte1 ......... 0018h intein/intad ...... 0020h intsr/intst ........ 0028h softi .................... 0060h (b) call address table the call address of a 1-byte call instruction (calt) can be stored in the 64-byte area (for 32 call ad- dresses) from address 0080h to address 00bfh. (c) specific memory area the reset start address, interrupt start addresses, and the call table are allocated to addresses 0000h to 00bfh, and this area takes account of these in use. addresses 0800h to 0fffh are directly addressable by a 2-byte call instruction (calf). the m pd78c18 has on-chip mask programmable rom in addresses 0000h to 7fffh. (d) internal data memory area 1-kbyte ram is incorporated in addresses fc00h to ffffh. the ram contents are retained for 1-kbyte internal data memory area in standby operation. (e) external memory area with the m pd78c17, the external memory can be expanded in steps in 63-kbyte area (0000h to fbffh) by setting the mode0 and mode1 pins (see table 2-3 ). with the m pd78c18, the external memory can be expanded in steps in 31-kbyte area (8000h to fbffh) by setting the memory mapping register (see fig. 2-13 ). the external memory is accessed using ad7 to ad0 (multiplexed address/data bus), ab7 to ab0 (ad- dress bus), and the rd, wr, and ale signals. both programs and data can be stored in the external memory. (f) working register area a 256-byte working register area can be set in any memory location (specified by the v register) and working register addressing is possible.
20 m pd78c17,78c18 fbffh fc00h ffffh 0080h 00bfh external memory 64512 8 bits internal ram note 1024 8 bits 0000h 0000h 0004h reset nmi 0008h intt0/intt1 0010h int1/int2 0018h inte0/inte1 0020h intein/intad 0028h intsr/intst 0060h softi low adrs high adrs low adrs high adrs low adrs high adrs 0081h 0082h 0083h 00beh t = 0 t = 1 t = 31 call table standby area fig. 2-3 m pd78c17 memory map note can only be used when the rae bit of the mm register is 1.
21 m pd78c17,78c18 fbffh fc00h ffffh 0080h 00bfh external memory 31744 8 bits internal ram note 1024 8 bits 0000h 0000h 0004h reset nmi 0008h intt0/intt1 0010h int1/int2 0018h inte0/inte1 0020h intein/intad 0028h intsr/intst 0060h softi low adrs high adrs low adrs high adrs low adrs high adrs 0081h 0082h 0083h 00beh t = 0 t = 1 t = 31 call table internal rom 32768 8 bits 7fffh 8000h 00c0h user's area 7fffh standby area fig. 2-4 m pd78c18 memory map note can only be used when the rae bit of the mm register is 1.
22 m pd78c17,78c18 2.5 port functions (1) pa7 to pa0 (port a) this is an 8-bit input/output port which has input/output buffer and output latch functions. port a can be set as to input or output bit-wise using the mode a register. and m pd78c18 port a pull-up resistor specification is performed bit-wise by mask option. port a is set as follows when setting the input port or after reset. high-impedance : without pull-up resistor high level : with pull-up resistor fig. 2-5 port a (a) when specified as output port (man = 0) the output latch is effective, enabling data exchange by a transfer instruction between the output latch and the accumulator. direct bit setting/resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. once data is written to the output latch, the data is held until a port a manipulation instruction is executed or the data is reset. fig. 2-6 port a specified as output port note only m pd78c18 v dd internal bus ma n latch wr m output latch wr p rd o rd i output buffer mask option note pa n v dd internal bus output latch wr p rd o mask option note pa n note only m pd78c18
23 m pd78c17,78c18 (b) when specified as input port (man = 1) pa line contents can be loaded into an accumulator by a transfer instruction. they can also be directly tested bit-wise by an arithmetic or logical operation instruction without the use of an accumulator. fig. 2-7 port a specified as input port actual execution of an instruction which manipulates port a is performed in 8-bit units. if a port a read instruction (mov a, pa) is executed, the input line contents of the port specified for input and the output latch contents of the port specified for output are loaded into an accumulator. when a port a write instruc- tion (mov pa, a) is executed, data is written to the output latch of both ports specified for input and output. however, the output latch contents of a bit specified as an input port cannot be loaded to the accumulator and are not output to an external pin (which functions as input pin), because the output buffer is off. ? mode a register (ma) 8-bit register which specifies port a input/output. port a input/output can be specified bit-wise. if the mode a register corresponding bit is set (1), this register is input, and if the bit is reset (0), this register is output. after reset input or in the hardware stop mode, all the bits are set, and port a is in the input mode resulting in the below status. high-impedance : without pull-up resistor high level : with pull-up resistor fig. 2-8 mode a register format 76543210 ma 7 ma 6 ma 5 ma 4 ma 3 ma 2 ma 1 ma 0 0 1 (n = 0 to 7) note only m pd78c18 pa n = output pa n = input v dd internal bus output latch wr p rd i mask option note pa n
24 m pd78c17,78c18 (2) pb7 to pb0 (port b) like port a, port b is an 8-bit input/output port with input/output buffer and output latch functions. port b can be set as an input or output port bit-wise using the mode b register (mb). m pd78c18 port b pull-up resistor specification is performed bit-wise by mask option. port b is set as follows when setting the input port or after reset. high-impedance : without pull-up resistor high level : with pull-up resistor as with port a, direct bit setting/resetting of port b output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. data transfer to/from an accumulator is also possible. ? mode b register (mb) like the mode a register, the mode b register is an 8-bit register which specifies port b input/ output bit-wise. after reset input or in the hardware stop mode, all the bits are set (1), and port b is in the input mode resulting in the status below. high-impedance : without pull-up resistor high level : with pull-up resistor fig. 2-9 mode b register format mb 7 mb 6 mb 5 mb 4 mb 3 mb 2 mb 1 (n = 0 to 7) pb n = output pb n = input mb 0 76543210 0 1
25 m pd78c17,78c18 mcc n = 1 mc n = x mcc n = 0 mcc n = 0 output output output output output output output output mc n = 1 input input input input input input input input t x d output r x d inpit sck input/output int2/ti input to output ci input co0 output co1 output pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 (3) pc7 to pc0 (port c) port c (pc7 to pc0) is an 8-bit special input/output port which functions as various control signals as well as general-purpose input/output ports in which input/output is set bit-wise like port a. these are switched over bit-wise according to the setting of the mode c register and mode control c register as shown below. table 2-2 operation of pc7 to pc0 (n = 0 to 7) m pd78c18 port c pull-up resistor specification is performed bit-wise by mask option. in the operation when data is set in the general-purpose input/output ports, as with port a, direct bit setting/resetting/testing of port c output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. data transfer to/from an accumulator is also possible. ? mode control c register (mcc) 8-bit register which specifies the port c port/ control signal input/output mode bit-wise. if the mode control c register corresponding bits are set (1), pc7 to pc0 are in the control signal input/output mode, and if these are reset (0), in the port mode. after reset input or in the hardware stop mode, all the bits of the mode control c register are reset (0), and the port mode is set.
26 m pd78c17,78c18 fig. 2-10 mode control c register format 76543210 mcc7 mcc6 mcc5 mcc4 mcc3 mcc2 mcc1 mcc0 pc0 = t x d output pc0 = port mode pc1 = port mode 1 pc1 = r x d input pc2 = sck input/output pc2= port mode 1 pc3 = port mode 1 pc3 = int2/ti input pc4= to output pc4 = port mode 1 pc7 = port mode 1 pc7 = co1 output pc6 = co0 output pc6= port mode 1 pc5 = port mode pc5 = ci input 0 1 0 0 0 0 0 1 0 0
27 m pd78c17,78c18 ? mode c register (mc) the mode c register is an 8-bit register by which, like the mode a register of port a, port c input/ output specification is performed bit-wise. contents of the mode c register corresponding to the bits set to the control mode by the mode control c register are ignored. after reset input or in the hardware stop mode, all bits of the mode c register are set (1). and this time, because all bits of the mode control c register are reset (0), port c becomes an input port and the below state is set. high-impedance : without pull-up resistor high level : with pull-up resistor fig. 2-11 mode c register format 76543210 mc 7 mc 6 mc 5 mc 4 mc 3 mc 2 mc 1 mc 0 (n = 0 to 7) (4) pd7 to pd0 (port d) n m pd78c17 can be used for address/data bus. these have no functions as a port. n m pd78c18 8-bit general-purpose input/output ports also used as multiplexed address/data bus. these ports can be specified for input/output in byte units (8-bit units) as general-purpose input/output ports, and function as multiplexed address/data bus when external expansion memory is connected. this switchover is per- formed by the memory mapping register. in the operation when data is set in the general-purpose input/output ports, unless input/output is specified in byte units, as with port a, direct bit setting/resetting/testing of port f output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. data transfer to/from an accumulator is also possible. pc n = output pc n = input 1 0
28 m pd78c17,78c18 when this is set as general-purpose input/output ports, as with port a, direct bit setting/resetting/ testing of port c output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. data transfer to/from an accumulator is also possible. ? m pd78c17 memory mapping register (mm) a register which controls internal ram access permission. bit 3 (rae) of the memory mapping register controls whether or not internal ram is permitted. when internal ram is used in external extension and external memory is used in the area, rae bit is set to 0 and internal ram access is prohibited. contents of rae bit is retained, even if reset signal is input in the normal operation. however, at power-on reset, rae bit is undefined and rae bit should be initialized by an instruction. fig. 2-12 m pd78c17 memory mapping register format (5) pf7 to pf0 (port f) n m pd78c17 general-purpose input/output ports also used as address bus. these pins function as address outputs corresponding to the size of externally installed memory accord- ing to the mode0 and mode1 pin settings. pins which are not used for address output can be used for general-purpose input/output ports which have the same port function as for port a. input/output setting is performed by the mode f register. table 2-3 operation of m pd78c17's pf7 to pf0 mode1 mode0 pf 7 pf 6 pf 5 pf 4 pf 3 pf 2 pf 1 pf 0 external address space 0 0 port port port port ab11 ab10 ab9 ab8 4 kbytes 0 1 port port ab13 ab12 ab11 ab10 ab9 ab8 16 kbytes 1 0 setting prohibited 1 1 ab15 ab14 ab13 ab12 ab11 ab10 ab9 ab8 63 kbytes 76543210 rae 0 0 0 internal ram access disable 0 enable 1
29 m pd78c17,78c18 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 external memory port port port port port port port port maximum 256 bytes port port port port ab11 ab10 ab9 ab8 maximum 4 kbytes port port ab13 ab12 ab11 ab10 ab9 ab8 maximum 16 kbytes ab15 ab14 ab13 ab12 ab11 ab10 ab9 ab8 maximum 31 kbytes n m pd78c18 8-bit general-purpose input/output ports also used as address bus. can specify input/output bit-wise as general-purpose input/output ports, and address signal is output according to external extension memory size when the external expansion memory of 256 bytes or greater is accessed. this switchover is performed by the memory mapping and mode f registers. when this is set as general-purpose input/ourput ports, as with port a, direct bit setting/resetting/testing of port c output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. data transfer to/from an accumulator is also possible. ? m pd78c18 memory mapping register (mm) 4-bit register which specifies pd7 to pd0 and pf7 to pf0 port/extension mode and controls internal ram access permission. bits 0, 1, and 2 (mm0, mm1, mm2) in the memory mapping register control specification of pd7 to pd0 port/extension mode, input/output, and pf7 to pf0 address line. when bits mm1 and mm2 in the memory mapping register are 0, pd7 to pd0 and pf7 to pf0 are set as general-purpose input/output port, input/output of pd7 to pd0 is specified by mm0, and input/output of pf7 to pf0 is specified by the mode f register. 4 types of external extension memory (256 bytes, 4 kbytes, 16 kbytes, and 31 kbytes) can be selected, and ports which are not used for address line are used as general-purpose input/output ports. bit 3 (rae) of the memory mapping register controls whether or not the access to internal ram is permitted. when internal ram is not used in external extension and external memory uses the area, rae bit is set to 0 and internal ram access is prohibited. after reset input or in the hardware stop mode, bits mm0, mm1, and mm2 of the memory mapping register are reset (0), and pd7 to pd0 become input ports (high-impedance). even if the reset signal is input in the normal operation, contents of the rae bit are retained. however, the rae bit is undefined after power-on reset, the rae bit should be initialized by an instruction.
30 m pd78c17,78c18 fig. 2-13 m pd78c18 memory mapping register format 76543210 rae mm2 mm1 mm0 0 0 0 0 1 0 port mode single chip pd7 to pd0 = extension mode pf7 to pf0 = port mode pd7 to pd0 = input port pf7 to pf0 = port mode pd7 to pd0 = output port pf7 to pf0 = port mode disable enable 1 internal ram access ? mode f register (mf) the mode f register specifies port f input/output in the same way as for the mode a register in port a. however, contents of the mode f register corresponding to port f bits specified as address line by the memory mapping register are in the output mode. after reset input or in the hardware stop mode, all the bits of the mode f register are set (1) and port f is an input port (high-impedance). fig. 2-14 mode f register format 76543210 mf 7 mf 6 mf 5 mf 4 mf 3 mf 2 mf 1 mf 0 0 (n = 0 to 7) extension mode extension mode extension mode exten- sion mode pd7 to pd0 = pf3 to pf0 = pf7 to pf4 = port mode pd7 to pd0 = pf5 to pf0 = pf7 and pf6 = port mode 16 kbytes 4 kbytes pd7 to pd0 = pf7 to pf0 = 0 10 1 1 0 256 bytes 1 00 31 kbytes 1 11 pf n = output pf n = input 0 1
31 m pd78c17,78c18 2.6 timer this is an interval timer which has two 8-bit timers (timer0, timer1). these are programmable indepen- dently. by cascading these can also be used as 16-bit interval timer, and can be used for counting ti input. the timer is composed of timer0 and timer1, as shown in 2-15, including 8-bit timer reg (tm0, tm1), 8- bit comparator, 8-bit upcounter, and timer f/f. input selection, timer operation and to output are controlled by the timer mode register (tmm). in timer0, f 12 (1 m s: 12-mhz operation) and f 384 (32 m s: 12-mhz operation) internal clock and ti input are input. in timer1, not only these inputs but also timer0 match signal are input. because timer0 operates in the same way as timer1, timer0 operation is described below. at first, a count value is set in timer reg0, and timer0 input and timer0 start data (bit 4 in the timer mode register = 0) are set in the timer mode register to start timer0. the upcounter is incremented one input at a time. the comparator always compares contents of the incremented upcounter with those of timer reg0, and if these match, the match signal (internal interrupt: intt0) is generated. this match clears contents of upcounter and increment starts again from 00h. therefore, the interval is set by count time, which is a count value set by timer reg0. this allows the timer to operate as an interval timer which gener- ates interrupts repeatedly. by setting (1) bit 1 (mkt0) of the interrupt mask register (mkl), internal interrupt (intt0) is disabled. the to output has timers comparator match signal and timer f/f complemented by f 3 (250 ns: 12-mhz operation) internal clocks, and can obtain a square wave which has a half period of the count time or f 3 . by setting the timer/event counter mode register (etmm), this output can be used for the timer event counter reference time. by setting the serial mode register (smh), the timer can be used as the serial clock (sck) in serial interface.
32 m pd78c17,78c18 internal bus upcounter comparator timer reg 0 (tm0) timer0 upcounter comparator timer reg 1 (tm1) timer1 intt0 clear clear intt1 timer f/f 3 timer/event counter serial interface pc4/to 12 384 12 384 pc3/ti f f f f f fig. 2-15 timer block diagram remarks 1. f 3 = f xx x 1/3 2. f 12 = f xx x 1/12 where, f xx = oscillation frequency (mhz) 3. f 384 = f xx x 1/384
33 m pd78c17,78c18 (1) timer mode register (tmm) this is an 8-bit register which controls timer0, timer1, and timer f/f operation (see fig. 2-16 ). the timer mode register bits 0 and 1 (tf0, tf1) control the timer f/f operating mode, bits 2 and 3 (ck00, ck01) control timer0 input clock, bit 4 (ts0) controls timer0 operation. bits 5 and 6 (ck10, ck11) control timer1 input clock, and bit 7 (ts1) controls timer1 operation. ts0 and ts1 bits clear these upcounters to 00h by 1, and stop increment. by changing 1 to 0, the upcounter starts increment from 00h. the internal clock ( f 3 ) divides the oscillator frequency by 3, the internal clock ( f 12 ) divides it by 12, and the internal clock ( f 384 ) divides it by 384. after reset input, the timer mode register is set to ffh, the upcounters in timer0 and timer1 are cleared in the suspended state, and timer f/f is reset. fig. 2-16 timer mode register (tmm) format 76543210 ts1 ck11 ck10 ts0 ck01 ck00 tf1 tf0 timer0 comparator match signal timer1 comparator match signal internal clock ( f 3 ) timer f/f reset 0 0 01 10 11 timer f/f input, operating mode tmm disable 0 0 0 1 10 11 timer0 input clock internal clock ( f 12 ) internal clock ( f 384 ) ti input timer0 operation reset increment 0 1 timer0 comparator match signal 0 0 01 10 11 timer0 input clock internal clock ( f 12 ) internal clock ( f 384 ) ti input timer1 operation reset increment 0 1
34 m pd78c17,78c18 2.7 timer/event counter the m pd78c17 and 78c18 have a 16-bit multi-function timer/event counter having the following functions. o interval timer o external event counter o frequency measurement o pulse width measurement o programmable square wave output o one pulse output the timer/event counters are composed of 16-bit timer/event counter upcounter (ecnt), timer/event counter capture register (ecpt), comparator, timer/event counter reg0 and reg1 (etm0, etm1), control circuits for i/o, interrupt, and clear. ecnt is a 16-bit upcounter which counts an input pulse, and cleared by the clear control circuit. the ecpt register is a 16-bit buffer register which retains the contents of ecnt. the timing to latch contents of ecnt by the ecpt register is the falling edge of ci input when input to ecnt is an internal clock, and is the falling edge of to output when input to ecnt is ci input. the etm0 and etm1 registers are two 16-bit registers which set a number of counts and data is exchanged by 16-bit data transfer instructions via an extended accumulator. the comparator compares contents of ecnt with contents of the etm0 and etm1 registers, and if these match, a match signal is generated. the interrupt control circuit controls interrupts from the timer/event counter. the following interrupt sources are generated. these are generated by three signals: the ecnt and etm0 register match signal (inte0), the ecnt and etm1 register match signal (inte1), and the ci input or timer output (to) falling edge (intein).
35 m pd78c17,78c18 timer/event counter capture reg. (ecpt) timer/event counter capture reg. (ecnt) input control clear control internal bus internal bus comparator timer/event counter reg1 (etm1) comparator timer/event counter reg0 (etm0) mode register (etmm, eom) edge detection ein cp1 cp0 output control interrupt control inte0 inte1 intein pc7/co1 pc6/co0 12 f pc5/ci to fig. 2-17 timer/event counter block diagram remarks f 12 = f xx x 1/12, where f xx = oscillation frequency (mhz)
36 m pd78c17,78c18 next, using pulse width measurement as an example, the operation is described. this operation purpose is measurement for high-level width of external pulse input to ci. this is performed by setting the timer/event counter mode register (etmm) to 09h. ecnt continues internal clock ( f 12 ) count while ci is high. if the external pulse which is input to ci falls, the contents of ecnt are transferred to the ecpt register. ecnt is cleared and an internal interrupt (intein) is generated (see fig. 2-18 ). therefore, using contents of the ecpt register and internal clock period, the pulse width is measured. fig. 2-18 pulse width measurement ci input reference clock ( f 12 ) ecnt input ein interrupt clear ecnt transfer ecnt contents to ecpt register
37 m pd78c17,78c18 the m pd78c17 and 78c18 have an output control circuit which outputs pulses which can be changed in pulse width and period by interlocking with the timer/event counter. the output control circuit outputs are co0 output and co1 output. because these share the same configura- tion, co0 output is described. fig. 2-19 shows the co0 configuration. co0 output is a master-slave type output. the first phase level f/f (lv0) retains the level which is output next, and the second phase output latch outputs the lv0 level to off-chip. by setting the timer/event counter output mode register (eom), lv0 can be set/reset. lv0 has a level inver- sion pin (inv) and lv0 level can be inverted at the output time by setting the timer/event counter mode regis- ter. timing when the output latch outputs lv0 level to off-chip is performed by output timing of the timer/event counter mode register setting. fig. 2-19 output control circuit pc6/co0 o ck r s inv q lv0 level flipflop lre1 output latch ld0 lo0 cp0 cp1 ci d lre0
38 m pd78c17,78c18 next, the operation which outputs a square wave to the co0 pin is described. at first, after ecnt is cleared, a count value (etm0 < etm1) is set in the etm0 and etm1 registers, and data for lv0 initial status specification and to enable lv0 level inversion is set in the timer/event counter output mode register. in the timer/event counter mode register, by setting an input to ecnt to f 12 (1 m s: 12-mhz operation) internal clock, the ecnt clear mode to the ecnt and etm1 register match signal, and co0 pin output timing to the ecnt and etm0 register match signal or ecnt and etm1 register match signal, the timer/event counter starts operation. ecnt is incremented one f 12 internal clock at a time, the comparator compares incremented ecnt with the etm0 and etm1 registers, and if these match, the match signal (cp0, cp1) is generated. by this match signal, lv0 level is output to the co0 pin, and lv0 level is inverted. ecnt is cleared by the ecnt and etm1 register match signal (cp1), ecnt increments again from 0000h, and the above-mentioned steps are repeated (see fig. 2-20 ). therefore, a programmable square wave which has the etm0 and etm1 register count as a pulse width is output. fig. 2-20 square wave output remarks etm0 register = m etm1 register = n (m < n: m and n are count values.) 0 reference clock ( f 12 ) cp0 cp1 co0 m n0 m n0 start
39 m pd78c17,78c18 (1) timer/event counter mode register (etmm) this is an 8-bit register which controls the timer/event counter (see fig. 2-21 ). the timer/event counter mode register bits 0 and 1 (et0, et1) control the timer event counter upcounter (ecnt) input clock, bits 2 and 3 (em0, em1) control the ecnt clear mode, bits 4 and 5 (co00, co01) control output timing when the output latch contents are output to the counter output0 (co0). bits 6 and 7 (co10, co11) control co1 output timing. the internal clock ( f 12 ) divides the oscillation frequency by 12. after reset input or in the hardware stop mode, the timer/event counter mode register is reset to 00h. fig. 2-21 timer/event counter mode register format 76543210 co11 co10 co01 co00 em 1 em 0 et 1 et 0 internal clock ( f 12 ) f 12 while ci input is in the high level ci input ci input while to is in the high level 0 0 0 1 10 11 ecnt input clock etmm 0 0 ecnt clear mode stop after clear free running clear a full count at a time 0 1 clear by matching ecnt and etm1 11 10 clear at the fall of ci input (et1 = 0) clear the fall of to (et1 = 1) 0 1 co0 output timing ecnt and etm0 match setting prohibited ecnt and etm0 match, or ci input fall 0 ecnt and etm0 match, or ecnt and etm1 match 01 co1 output timing ecnt and etm1 match setting prohibited ecnt and etm1 match, or ci input fall 10 ecnt and etm0 match, or ecnt and etm1 match 00 1 1 0 1 0 1 1
40 m pd78c17,78c18 (2) timer/event counter output mode register (eom) this is an 8-bit register which controls the timer/event counters co0 and co1 (counter output 0, 1) operating mode. the timer/event counter output mode register bits 0 and 4 (lo0, lo1) control whether or not lv0 and lv1 level are output to the co0 and co1 pins, bits 1 and 5 (ld0, ld1) control whether or not lv0 and lv1 level are inverted at an output timing specified by the timer/event counter mode register, bits 2, 3, 6, and 7 (lre0, lre1, lre2, lre3) control lv0 and lv1 setting/resetting. bits lo0, lo1, lre0, lre1, lre2, and lre3 are automatically reset (0) after individual operations. after reset input or in the hardware stop mode, the timer/event counter output mode register is reset to 00h. fig. 2-22 timer/event counter output mode register (eom) format 76543210 lre3 lre2 ld 1 lo 1 lre1 lre0 ld 0 lo 0 lv0 data output output contents of lv0 no operation 0 1 lv0 level inversion enable disable 0 1 setting prohibited 10 11 lv0 set/reset no operation resets lv0 sets lv0 lv1data output output contents of lv1 no operation lv1 level inversion enable disable 0 1 setting prohibited lv1 set/reset no operation resets lv1 sets lv1 1 0 0 0 0 1 0 0 1 1 0 1 0 1
41 m pd78c17,78c18 2.8 serial interface the m pd78c17 and 78c18 have the serial interface using the transmit/receive method by start/stop bit. the three types of operating modes are shown below. ? asynchronous (start-stop) mode : establishes data bit synchronization and character synchronization by start bit. ? synchronous mode : data transfer is performed in synchronization with the serial clock. ? i/o interface mode : as for serial data transfer in the m pd7801/78c06a etc., data transfer is performed in synchronization with the serial clock. the serial interface block is composed of the serial data input (rxd), serial data output (txd), 3 serial clock input/output (sck) pins, transfer control block, two 8-bit serial registers for transmission and reception, and 8- bit transmission buffer and reception buffer (see fig. 2-23 ). as the serial registers and buffers for transmission and reception are provided, transmission or reception is individually performed (full-duplex double buffer transmitter/receiver). however, the serial clock (sck) is shared in transmission and reception, and half-duplex transmission/ reception is performed in the synchronous mode and i/o mode. fig. 2-23 serial interface block diagram remarks f 24 = f xx x 1/24 where, f xx = oscillation frequency (mhz) f 384 = f xx x 1/384 internal bus intsr receive buffer (rxb) serial mode register (sml, smh) transmit buffer (txb) serial register (s ? p) serial register (p ? s) pc1/r d pc2/sck sk1, sk2 f 24 f 384 to output pc0/t d er control reception transmission control intst
42 m pd78c17,78c18 start bit d0 d1 dn parity bit stop bit n = 6, 7 (1) asynchronous mode in case of the asynchronous mode, clock rate, character length, number of stop bits, parity enable, and odd or even parity specifications can be controlled by the serial mode register (sml). transmission operation is enabled by setting (1) bit 2 (txe) of the serial mode register (smh). if data is written to the transmission buffer by the mov txb, a instruction and preceding data transfer is terminated, contents of the transmission buffer are transferred to the serial register automatically. the start bit (1 bit), parity bit (odd/even number, no parity), and stop bit (1 or 2 bits) are automatically added to data which is transferred to the serial register. and this data is transmitted from the txd pin starting from the least significant bit (lsb). if the transmit buffer is empty, the internal interrupt (intst) is generated. transmission data is transmitted from the txd pin at the fall of sck in the transfer speed of x1, x1/16, or x1/64 serial clock (sck). the maximum data transfer speed in transmission is set by sck and clock rate in 12-mhz operation as shown below. when txe is 0 or the serial register has no transmitted data, the txd pin is in the marking state (1). by setting bit 2 (mkst) of the interrupt mask register (mkh), the internal interrupt (intst) is disabled. fig. 2-24 asynchronous data format internal clock data transfer speed external clock data transfer speed sck sck clock rate sck x1 x16 x64 500 kbps 125 kbps 31.25 kbps 660 kbps 125 kbps 31.25 kbps 500 khz 660 khz 2 mhz 2 mhz
43 m pd78c17,78c18 0 0 1 1 0 1 0 1 fig. 2-25 serial mode register format in asynchronous mode 76543210 s 2 s1 ep pen l 2 l 1 b 2 b 1 sml x1 x16 x64 clock rate character length 8 bits setting prohibited setting prohibited 7 bits 0 1 parity enable disable enable 0 1 even parity generation/check odd number even number number of stop bits 2 bits setting prohibited 1 bit setting prohibited 76543210 0 0 0 0 rxe txe sk2 sk1 smh sck selection external clock internal clock (to output) internal clock ( f 384 ) internal clock ( f 24 ) transmission enable reception enable 0 1 1 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 disable enable enable disable
44 m pd78c17,78c18 receive operation is enabled by setting (1) bit 3 (rxe) of the serial mode register (smh). the start bit is confirmed by detecting the low level of rxd input and the low level after 1 or 2 bits. reception is performed by sampling character bit, parity bit, and stop bit following the low level. when data specified in the serial register from rxd is input, data is transferred to the receive buffer. if the receive buffer is full, the internal interrupt (intsr) is generated. by setting (1) bit 1 (mksr) of the interrupt mask register (mkh), the internal interrupt (intsr) is disabled. in reception, odd or even parity is checked (when pen bit = 1). if data do not match (parity error), if stop bit is low (framing error), or if the next data is transferred to the receive buffer when the receive buffer is full (overrun error), the error flag is set (1). however, because error interrupt mechanism is not provided, test is executed by the skip instruction (skit, sknit). the serial clock (sck) can be selected as an external or internal clock by the serial mode register (smh). three types of f 24 , f 384 , or to outputs can be selected as internal clock. this clock can be output to off- chip. or the external serial clock can be input. by using the internal clock (to output) as sck, the data transfer speed can be flexibly changed by program. the maximum data transfer speed in reception is set by sck and the clock rate in 12-mhz operation as shown below. internal clock data transfer speed external clock data transfer speed sck sck clock rate sck 500 kbps 125 kbps 31.25 kbps 125 kbps 31.25 kbps 500 khz 2 mhz 2 mhz 660 khz 1 mhz 660 kbps 1 mbps note1 notes 1. if data of transfer speed 660 kbps to 1 mbps is received, 2 stop bits are required. 2. in x1 clock rate, rxd and sck synchronization needs to be externally established. for an example, when data is transferred in the data transfer speed of 110 to 9600 bps, when the timer input clock is set as internal clock ( f 12 ), the timer count value (c) is shown below. data transfer speed (bps) oscillation frequency (mhz) n 7.3728 14.7456 11.0592 64 16 64 16 16 64 9600 4800 2400 1200 600 300 150 110 2 4 8 16 32 64 128 175 c = C 1 2 4 8 16 32 44 c = 3 6 12 24 48 96 192 262 C C 3 6 12 24 48 65 c = 4 8 16 32 64 128 256 370 1 2 4 8 16 32 64 88 c = c = c = x1 note2 x16 x64
45 m pd78c17,78c18 (2) synchronous mode in the synchronous mode, data transfer is performed with 8-bit character length fixed, and with no parity bit. therefore, the serial mode register (sml) is set to 0ch (see fig. 2-26 ). transmission operation is enabled by setting (1) bit 3 (txe) of the serial mode register (smh). if data is written to the transmit buffer by the mov txb, a instruction and preceding data transfer is terminated, the contents of the transmit buffer are automatically transferred to the serial register and converted to serial data, and data starting from lsb are transmitted from txd at the falling edge of sck. the serial data is transferred in the same rate as for sck. data transfer speed in transmission is maximum 500 kbps when an internal clock is used for sck and maximum 1 mbps when an external clock is used (12-mhz operation). when data is transferred from the transmit buffer to the serial register and the transmit buffer is empty, the internal interrupt (intst) is generated. when txe is 0 or the serial register has no transmitted data, the txd pin is in the marking state (1). fig. 2-26 serial mode register format in synchronous mode 76543210 00001100 sml synchronous operation character length 8-bit fixed parity disable 76543210 0 0 0 se rxe txe sk 1 smh sck selection external clock internal clock (to output) internal clock ( f 384 ) internal clock ( f 24 ) transmission enable 0 1 reception enable disable enable sk 2 0 1 search mode disable enable 0 0 1 1 0 1 0 1 disable 0 enable 1
46 m pd78c17,78c18 in the synchronous mode, 2 types of receive operation can be selected. this mode can be controlled by se bit of the serial mode register (smh). by setting se bit (1), the search mode is set. on each 1-bit reception from the rxd pin, the contents of the serial register are transferred to the receive buffer and the internal interrupt (intsr) is generated. because the m pd78c17(a)/78c18(a) don't have a synchronous character detection circuit by hardware, a synchronous character detection is required by software. if receive synchronization is established after a synchronous character is detected, se bit is reset (0). by resetting the se bit, the character mode is set. on each 8-bit data reception, the contents of the serial register are transferred to the receive buffer and the internal interrupt (intsr) is generated. by setting (1) mksr bit of the interrupt mask register, the internal interrupt (intsr) is disabled. in the synchronous mode, data is output from txd at the falling edge of sck, and data is input from rxd at the rising edge of sck. sck can be selected as an internal clock or external clock by setting the serial mode register (smh). data transfer speed in reception is maximum 500 kbps when an internal clock is used for sck and maximum 660 kbps when an external clock is used (12-mhz operation).
47 m pd78c17,78c18 (3) i/o interface mode when input/output is extended to off-chip or i/o controllers (a/d converter, liquid crystal display controller, etc.) are connected to this chip, this mode is effective. in the i/o interface mode, data transfer is performed starting from the most significant bit (msb) with 8-bit character length fixed, and with no parity bits. therefore, the serial mode register (sml) should be set to 0ch and bit 5 (ioe) of the serial mode register (smh) is set to 1. this mode establishes synchronization by controlled sck (8 cycles of the serial clock) and sck should be high except during data transfer. the transmission operation is enabled by setting (1) bit 2 (txe) of the serial mode register (smh). if data is written by the mov txb, a instruction, data is transferred to the serial register automati- cally, and is output from txd at the falling edge of controlled sck. the transmit buffer is empty, the internal interrupt (intst) is generated. data transfer speed in transmission is maximum 500 kbps when an internal clock is used for sck and maximum 1 mbps when an external clock is used (12-mhz operation). the reception operation is enabled by setting (1) bit 3 (rxe) of the serial mode register (smh), and receive data is input to the serial register at the rising edge of controlled sck. when the serial register receives 8-bit data, data is transferred from the serial register to the receive buffer and the internal inter- rupt (intsr) is generated. sck can be selected as an internal clock or external clock by the serial mode register (smh). data transfer speed in reception is maximum 500 kbps when an internal clock is used for sck and maximum 660 kbps when an external clock is used for sck (12-mhz operation). 6 states or more is re- quired in 8th sck high-level width.
48 m pd78c17,78c18 fig. 2-27 serial mode register format in i/o interface mode 76543210 00001100 sml synchronous operation character length 8-bit fixed parity disable 76543210 0 tsk 1 0 rxe txe sk 1 smh sck selection external clock internal clock (to output) internal clock ( f 384 ) internal clock ( f 24 ) transmission enable 0 1 reception enable disable enable sk 2 i/o interface mode 0 1 sck trigger disable enable 0 0 1 1 0 1 0 1 disable 1 enable 0
49 m pd78c17,78c18 (4) serial mode register (sml, smh) these are two 8-bit registers which control the serial interface operation (see figs. 2-28 and 2-29 ). the serial mode low register (sml) bits 0 and 1 (b1, b2) control switchover of the asynchronous mode and synchronous operation and clock rate in the asynchronous mode, bits 2 and 3 (l1, l2) control charac- ter length, bit 4 (pen) controls parity enable, bit 5 (ep) controls odd or even parity, and bits 6 and 7 (s1, s2) control a number of stop bits. after reset input or in the hardware stop mode, the serial mode low register (sml) is set to 48h. the serial mode high register (smh) bits 0 and 1 (sk1, sk2) control whether an internal clock or external clock is used as the serial clock (sck), bit 2 (txe) controls the transmission operation, bit 3 (rxe) controls the reception operation, bit 4 (se) controls whether or not the search mode is set in the synchro- nous mode. bit 5 (ioe) controls whether the synchronous mode or i/o interface mode is set, and bit 6 (tsk) starts the serial clock when data is received using the internal clock in the i/o interface mode. the tsk bit is automatically reset (0) after the serial clock starts. when the serial clock is specified as an internal clock, the sck value is determined by the following expressions. internal clock ( f 24 ): sck = f xx /24 internal clock ( f 384 ): sck = f xx /384 internal clock (to output): timer input clock is f 12 : sck = f xx /(24 x c) timer input clock is f 384 : sck = f xx /(768 x c) timer f/f input is f 3 : sck = f xx /6 however, f xx is set in the oscillation frequency, sck is set in the serial clock, and c is set in the timer count value. when timer f/f input is f 3 in case of the internal clock (to output), the asynchronous mode can only be used when the clock rate is 16 or 64. after reset input or in the hardware stop mode, the serial mode high register (smh) is reset to 00h.
50 m pd78c17,78c18 fig. 2-28 serial mode low register (sml) format 76543210 s 2 s1 ep pen l 2 l 1 b 2 b 1 0 clock rate x 1 x 16 x 64 synchronous operation 10 11 0 1 0 character length 8 bits 0 0 0 1 10 11 setting prohibited setting prohibited 7 bits parity enable 0 1 disable enable 0 1 even parity generation/check odd number even number number of stop bits 2 bits 0 0 0 1 10 11 setting prohibited 1 bit setting prohibited
51 m pd78c17,78c18 fig. 2-29 serial mode high register (smh) format 76543210 0 tsk ioe se rxe txe sk 1 sck selection external clock 0 0 01 10 11 internal clock (to output) internal clock ( f 384 ) internal clock ( f 24 ) sk 2 transmission enable 0 1 disable enable 0 1 reception enable disable enable 0 1 search mode disable enable 0 1 i/o interface mode disable enable 0 1 sck trigger disable enable
52 m pd78c17,78c18 2.9 analog/digital converter the m pd78c17 and 78c18 have on-chip 8-bit high-speed and high-resolution analog/digital (a/d) converter with 8-multiplexed analog input (an7 to an0), and 4 conversion result registers (cr0 to cr3) to retain a conversion result. this a/d converter uses the successive approximation method. in the a/d converter operation, either the scan mode or select mode can be selected by software. in the select mode, one of analog inputs is selected by the a/d channel mode register before starting a/d conversion. conversion values are stored to cr0 through cr3 sequentially. in the scan mode, analog conver- sion values an0 to an3 or an4 to an7 are stored to cr0 through cr3 sequentially. this mode switchover is specified by the a/d channel mode register. in case of the select mode, one of the analog inputs is selected by the a/d channel mode register and the a/ d conversion starts. conversion values are stored to cr0 through cr3 sequentially. when four cr registers are set to conversion values, the internal interrupt (intad) is generated. the a/d converter continues a/d conver- sion and sequential storage of conversion values beginning with cr0 until the a/d channel mode register is changed. in case of the scan mode, the analog input an0 to an3 (ani2 = 0) or an4 to an7 (ani2 = 1) can be selected. if bit 3 (ani2) of the a/d channel mode register is set to 0, analog inputs an0, an1, an2, an3 and an0 are selected in that order. these input a/d conversion values cr0, cr1, cr2, cr3, and cr0 are stored in that order. if ani2 of the a/d channel mode register is set to 1, analog inputs an4, an5, an6, an7, and an4 are selected in that order, and these input a/d conversion values cr0, cr1, cr2, cr3, and cr0 in that order. in the scan mode, like in the select mode, when four cr registers are set to conversion values, the internal interrupt (intad) is generated. in the scan mode, too, the above-mentioned operation is repeated until the a/d channel mode register is changed. by setting (1) bit 0 (mkad) of the interrupt mask register (mkh), the internal interrupt (intad) is disabled.
53 m pd78c17,78c18 fig. 2-30 a/d converter block diagram caution capacitors should be connected to the analog input pins and reference voltage input pins in order to prevent mulfunction due to noise. internal bus cr0 8 8 cr1 8 8 cr2 8 8 cr3 8 8 8 a/d converter multiplexer an0 an1 an2 an3 an4 an5 an6 an7 av av v dd ss aref av ss v ss v aref an n m pd78c17 m pd78c18 100 to 1000 pf analog input 100 to 1000 pf reference voltage input
54 m pd78c17,78c18 an0 an1 an2 an3 an4 an5 an6 an7 (1) a/d channel mode register (anm) this is an 8-bit register which controls a/d converter operation. bit 0 (ms) of the a/d channel mode register controls the operating mode, bits 1, 2, and 3 (ani0, ani1, ani2) controls a/d conversion input, and bit 4 (fr) controls a/d operation according to change of the oscillator frequency. in the a/d channel mode register, the operating mode specification is written, and the contents of this register are read. therefore, in the a/d interrupt generation, analog input data distinction is possible. after reset input or in the hardware stop mode, the a/d channel mode register is set to 00h. fig. 2-31 a/d channel mode register format 76543210 fr ani2 ani1 ani0 ms operating mode specification select mode scan mode 0 1 1 0 1 0 11 11 0 0 00 01 01 0 1 0 1 0 1 0 1 analog input specification oscillator frequency 9 mhz (144 states) 1 oscillator frequency > 9 mhz (192 states) 0 (2) a/d converter operation control method the a/d converter can stop conversion operation by controlling the v aref input voltage. if a voltage greater than v ih1 is input to the v aref pin, the a/d converter starts conversion operation and the conversion results are guaranteed in v aref = 3.4 v to av dd . if the v aref pin input voltage is set to less than v il1 during the conversion operation, the a/d converter conversion operation stops. at this time, contents of cr0 to cr3 are undefined. even if the v aref input voltage is changed for a/d converter stop control, the a/d channel mode register (anm) is not affected. therefore, if the v aref input voltage is greater than 3.4 v, the a/d converter restarts operation beginning with storage of conversion values to cr0 in the mode directly before the stop state is set. even if the v aref input voltage level is changed, the detection function of an4 to an7 input edge is not affected. caution when v aref is low, inputs an0 to an7 in the range of av ss to av dd are necessary.
55 m pd78c17,78c18 2.10 zero-cross detector the int1 pin and int2/ti (shared as pc3) pin can be made to execute zero-cross detection operations by setting the zero-cross mode register. the zero-cross detector has a self-bias type high-gain amplifier. it biases the input to the switching point and generates digital displacement in response to a small input displacement. fig. 2-32 zero-cross detector the zero-cross detector detects a negative-to-positive or positive-to-negative transition of the ac signal input through an external capacitor and generates a digital pulse which changes from 0 to 1 or 1 to 0 at each transition point. fig. 2-33 zero-cross detection signal ac input signal zero-cross detection signal to internal circuit self bias circuit enable int 1 int 2 / ti 1 f external capacitor ac input signal m pd78c17, 78c18 m
56 m pd78c17,78c18 a digital pulse generated in the zero-cross detector of the int1 pin is sent to the interrupt control circuit. the intf1 interrupt request flag is set at the zero-cross point from the negative to the positive state of the ac signal (rising edge), and if int1 interrupt is enabled, interrupt servicing is started. a digital pulse generated in the int2/ti pin zero-cross detector is sent to the interrupt control circuit and interrupt servicing can be started at the zero-cross point from the positive to the negative state of the ac signal (falling edge) as with the int1 pin, and can also be used as a timer input clock. the format of the zero-cross mode register (zcm), which controls self-bias for zero-cross detection of the int1 and int2/ti pins, is shown in fig. 2-34. fig. 2-34 zero-cross mode register format 76543210 zc2 zc1 int1 pin generates self-bias does not generate self-bias 0 1 zcm int2/t1 pin generates self-bias does not generate self bias 0 1 when the zc1 and zc2 bits of the zero-cross mode register are set to 0, a self-bias for zero-cross detection of each pin is not generated and each pin responds as a normal digital input. when the zc1 and zc2 bits are set to 1, a self-bias is generated and an ac input signal zero-cross can be detected by connecting a capacitor to each pin. each pin with zc1 and zc2 bits set to 1 can be directly driven without the use of an external capacitor. in this case, each pin responds as a digital input. however, an input load current is necessary and an external circuit output driver must be considered. thus, when no zero-cross detection is executed and each pin is used simply as an interrupt input or timer input, the zc1 and zc2 bits of the zero-cross mode register should be set to 0. reset input sets both the zc1 and zc2 bits to 1 and a self-bias is generated. the zero-cross function of the int2/ti (shared as pc3) pin can operate only when the control mode is specified by the mode control c register (mcc). in the port mode, the zero-cross detection function does not operate. caution unlike other cmos circuits, a supply current is always present in the zero-cross detector because of its operation points. this also applies in the standby modes (halt and software/hardware stop modes). thus, when the zero-cross detector is operated (with self-bias generation: zcx = 1), slightly more current flows than without zero-cross detector operation, and its effect is greater in the software/hardware stop mode.
57 m pd78c17,78c18 interrupt external/ priority interrupt request address internal 1 4 nmi falling edge external 2 8 intt0 match signal from timer0 internal intt1 match signal from timer1 3 16 int1 rising edge external int2 falling edge 4 24 inte0 match signal from timer/event counter internal inte1 match signal from timer/event counter 5 32 intein ci pin or to fall signal internal intad a/d converter interrupt 6 40 intsr serial reception interrupt internal intst serial transmission interrupt 3. interrupt functions there are 3 kinds of external interrupt request and 8 kinds of internal interrupt requests. the 11 kinds of interrupt requests are divided into 6 groups, each of which is assigned a different priority and interrupt ad- dress. the priority of these interrupt sources and interrupt addresses are as follows.
58 m pd78c17,78c18 3.1 interrupt control circuit configuration the interrupt control circuit consists of a request register, a mask register, a priority control, a test control, an interrupt enable f/f, and a test flag register (see fig. 3-1 ). fig. 3-1 interrupt control circuit block diagram nmi intt0 intt1 int1 int2 inte0 inte1 intein intad intsr intst ov er an7 to an4 sb test flag register t.f intfnmi mask register t.f intfnmi test control priority control softi int. adr ei di s r q enable softi intfnmi internal bus interrupt generation request register skip control
59 m pd78c17,78c18 (a) request register this register consists of 11 interrupt request flags which are set by the different interrupt requests. a flag is reset when an interrupt request is acknowledged or a skip instruction (skit or sknit) is executed. reset input resets all flags. there are 11 types of interrupt request flags. ? intfnmi set (1) by a falling edge input to the nmi pin. unlike other interrupt request flags, this flag cannot be tested by a skip instruction. ? intft0 set (1) by timer0 comparator match signal. ? intft1 set (1) by timer1 comparator match signal. ? intf1 set (1) by a rising edge input to the int1 pin. ? intf2 set (1) by a falling edge input to the int2 pin. ? intfe0 set (1) by a match signal when timer/event counter ecnt and etm0 register contents match. ? intfe1 set (1) by a match signal when timer/event counter ecnt and etm1 register contents match. ? intfein set (1) by a falling edge of the timer/event counter ci input or timer output (to). ? intfad set (1) when a/d converter conversion values are transferred to the four registers cr0 to cr3. ? intfsr set (1) when the serial interface receive buffer becomes full. ? intfst set (1) when the serial interface transmit buffer becomes empty. (b) mask register this is a 10-bit mask register which handles all interrupt requests except non-maskable interrupts (nmi). it can be set (1) or reset (0) bit-wise by an instruction. an interrupt request is masked (disabled) or enabled when the corresponding bit of the mask register is 1 or 0, respectively. all bits of the mask register are set by reset input and all interrupt requests except non-maskable inter- rupts are masked. all bits of the mask register are set in the hardware stop mode.
60 m pd78c17,78c18 fig. 3-2 mask register (mkl, mkh) format 0 1 intst mask release intst mask 0 1 intsr mask release intsr mask 0 1 intad mask release intad mask 6 mke1 5 mke0 4 mk2 3 mk1 2 mkt1 1 mkt0 0 7 mkein mkl 0 1 intt0 mask release intt0 mask 0 1 intt1 mask release intt1 mask 0 1 int1 mask release int1 mask 0 1 int2 mask release int2 mask 0 1 inte0 mask release inte0 mask 0 1 inte1 mask release inte1 mask 0 1 intein mask release intein mask 6 5 4 3 2 mkst 1 mksr 0 mkad 7 mkh
61 m pd78c17,78c18 (c) priority control circuit this circuit controls the 6 priority levels described earlier. if two or more interrupt request flags are set simultaneously, the interrupt with the highest priority according to the priority is acknowledged. (d) test control circuit this circuit comes into operation when a skip instruction (skit or sknit) is executed to test interrupt request flags (except intfnmi) for each interrupt source, nmi pin states, and test flags. (e) interrupt enable f/f (ie f/f) this is a flip-flop which is set by the ei instruction and reset by the di instruction. this flip-flop is reset when an interrupt is acknowledged, and by reset input, too. interrupts are enabled when this flip-flop is set, and disabled when it is reset. (f) test flag register this register consists of 7 test flags which do not generate interrupt requests. these flags are tested or reset by the skip instructions (skit, sknit). ?ov set (1) when the timer/event counter ecnt overflows. ?er set (1) in the event of a parity error, framing error or overrun error in serial interface. ?sb set (1) if v dd pin increases from a level lower than specified to a level higher than specified. ? an7 to an4 set (1) by a falling edge input to pins an7 to an4. 3.2 non-maskable interrupt operation when the interrupt request flag (intfnmi) is set by a falling edge input to the nmi pin, a non-maskable interrupt is acknowledged by means of the following procedure irrespective of the ei/di state (see fig. 3-3 ). (i) a check is made to see if intfnmi is set at the end of each instruction. if intfnmi is set, a non- maskable interrupt is acknowledged and intfnmi is reset. (ii) when the non-maskable interrupt is acknowledged, the ie f/f is reset and all interrupts except for non- maskable interrupts and the softi instruction are placed in the disabled state (di state). (iii) psw, pc high byte, and pc low byte are saved into the stack memory in that order. (iv) the program jumps to the interrupt address (0004h). these interrupt operations are automatically carried out in 16 states. the interrupt request flag (intfnmi) cannot be tested by the skip instruction. however, the nmi pin status can be tested by the skip instruction (skit nmi, sknit nmi). therefore, by testing the nmi pin status with the skip instructions in several times in the non-maskable interrupt service routine, noise of comparatively long period or periodical noise can be removed. the nmi pin status is not changed even if the status is tested by the skip instruction.
62 m pd78c17,78c18 fig. 3-3 interrupt operation procedure nmi? n di status? all masked? n n unmasked intf check number of set flags 2 or more 0 1 y n y y y intfnmi reset other interrupts hold priority check highest priority interrupt both interrupts of the same level are non-masked? intf reset next instruction ie f/f reset psw and pc saved to stack memory pc ? interrupt address instruction end
63 m pd78c17,78c18 3.3 maskable interrupt operation interrupt requests except non-maskable interrupts and the softi instruction are maskable interrupts which can be enabled/disabled (ie f/f set/reset) by the ei/di instructions and can be masked individually by means of the mask register. when an external maskable interrupt is recognized as a normal interrupt signal by an active level input for more than the specified time, an interrupt request flag is set. if an internal interrupt request is generated, an interrupt request flag is immediately set. once the interrupt request flag is set, both the external and internal interrupts are serviced using the following procedure (see fig. 3-3 ). (i) in the ei state (ie f/f = 1), a check is made to see if the interrupt request flag has been set at the end checked at end of each instruction. if the flag has been set, the interrupt cycle starts. however, interrupt requests masked by the mask register are not checked. (ii) if two or more interrupt request flags have been set simultaneously, their priorities are checked. the interrupt with the highest priority is acknowledged and the others are held pending. (iii) when an interrupt request is acknowledged, the interrupt request flag is automatically reset. if two types of interrupt requests with the same priority have both been unmasked by the mask register, the interrupt request flag is not reset. this is because the two types are identified by software at a later stage. (iv) when an interrupt request is acknowledged, the ie f/f is reset, and all interrupts except non-maskable interrupts and the softi instruction are placed in the disabled state (di state). (v) the psw, upper pc byte, and lower pc byte are saved to the stack memory in that order. (vi) the program jumps to the interrupt address. these interrupt operations are automatically carried out in 16 states. the pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority when interrupts are enabled by execution of the ei instruction. with maskable interrupts there are two types of interrupt requests with the same priority and same interrupt address. unmasking both types, unmasking one type, or masking both kinds can be selected by setting the mask register. (1) when both types are unmasked the corresponding bits of the mask register for two types of interrupt requests are both set to 0. in this case, the interrupt request is the logical sum of the two interrupt request flags. if an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one or both interrupt request flags having the same priority and the program jumps to the interrupt address, the interrupt request flag is not reset. therefore, the interrupt request is identified by executing a skip instruction which tests the interrupt request flag at the beginning of the interrupt service routine, and the interrupt request flag is reset. (2) when one type is unmasked for two types of interrupt requests having the same priority, the corresponding bit of the mask register for the interrupt request to be unmasked is set to 0 and the other bit is set to 1. in this case, if an interrupt request is generated by setting the unmasked interrupt request flag and that interrupt request is acknowledged in accordance with the interrupt operation, the interrupt request flag is automatically reset. when the masked interrupt request flag is set, that interrupt request is held pending. when the pending interrupt request is unmasked, it is acknowledged if there are no other interrupt requests of higher priority in the interrupt enable state. (3) when both types are masked the corresponding bits of the mask register for two types of interrupt request are both set to 1. in this case, the interrupt requests are held pending are not acknowledged when the interrupt request flag is set. when the pending interrupt requests are unmasked, they are acknowledged if there are no other interrupt requests of higher priority in the interrupt enabled state.
64 m pd78c17,78c18 3.4 interrupt operation by softi instruction when the softi instruction is executed, the program jumps unconditionally to the interrupt address (0060h). the softi instruction interrupt is not affected by the ie f/f, and the ie f/f is not affected when this instruction is executed. the servicing procedure for an interrupt generated by the softi instruction is as follows: (i) the psw, upper pc byte, and lower pc byte are saved to the stack memory in that order. (ii) the program jumps to the interrupt address (0060h). caution if the skip condition is satisfied by the instruction (arithmetic or logical operation, increment/ decrement, shift, skip, or rets instruction) immediately before the softi instruction, the softi instruction is executed and not skipped. when softi instruction is executed, the sk flag of the psw is saved as set (1) to the stack area. thus, when the return is made from the softi service routine, the psw sk flag remains set and the instruction following the softi instruction is skipped.
65 m pd78c17,78c18 4. standby functions three standby modes are available for the m pd78c17 and 78c18 to save power consumption in the program standby mode (the halt mode, software stop mode, and hardware stop mode). 4.1 halt mode when the hlt instruction is executed, the halt mode is set unless the interrupt request flag of the un- masked interrupt is set. in the halt mode the cpu clock stops and program execution also stops. however, the contents of all registers and internal ram just before the stoppage are retained. in the halt mode, the timer, timer/event counter, serial interface, a/d converter, and interrupt control circuit are operational. table 4-1 shows the status of the m pd78c17 and 78c18 output pins in the halt mode. table 4-1 output pin statuses output pin single chip note1 external expansion pa7 to pa0 data retained data retained pb7 to pb0 data retained data retained pc7 to pc0 data retained data retained pd7 to pd0 data retained high-impedance pf7 to pf0 data retained next address retained note2 data retained note3 wr, rd high-level high-level ale high-level high-level notes 1. m pd78c18 only 2. address output pin 3. port data output pin caution because an interrupt request flag is used to release the halt mode, hlt instruction execution does not set the halt mode if even a single interrupt request flag for an unmasked interrupt is set. thus, when setting the halt mode when there is a possibility that an interrupt request flag may have been set (when there is a pending interrupt), one of the following procedures should be followed: first process the pending interrupt; or, reset the interrupt request flag by executing a skip instruction; or, mask all interrupts except those used to release the halt mode.
66 m pd78c17,78c18 4.2 halt mode release (1) release by reset signal when the reset signal changes from the high to low level in the halt mode, the halt mode is released and the reset state is set. when the reset signal returns to the high level, the cpu starts program execution at address 0. when the reset signal is input, the ram contents are retained but the contents of other registers are undefined. fig. 4-1 halt mode release timing (reset signal input) cpu osc reset halt address 0 instruction execution
67 m pd78c17,78c18 (2) release by interrupt request flag the halt mode is released if at least one interrupt request flag is set by the generation of a non-maskable interrupt (nmi) or one of ten unmasked maskable interrupts (intt0, intt1, int1, int2, inte0, inte1, intein, intad, intst, and intsr). when the halt mode is released by a non-maskable interrupt, the instruction following the hlt instruction is not executed and the program jumps to the interrupt address (0004h) irrespective of the interrupt enabled/ disabled (ei/di) state. when the halt mode is released by a maskable interrupt, operation after release differs depending on whether the ei or di state is set. (i) ei state the instruction following the hlt instruction is not executed and the program jumps to the corresponding interrupt address. fig. 4-2 halt mode release timing (in ei state) cpu operation osc intf hlt interrupt execution interrupt routine (ii) di state execution restarts with the instruction following the hlt instruction (without jumping to the interrupt address). because the interrupt request flag used for release remains set, it should be reset by a skip instruction when required. fig. 4-3 halt mode release timing (in di state) cpu operation osc intf hlt following instruction execution
68 m pd78c17,78c18 4.3 software stop mode when the stop instruction is executed, the software stop mode is set unless the interrupt request flag for an unmasked external interrupt is set. in the software stop mode, all clocks stop. when this mode is set, program execution stops and the contents of all registers and internal ram are retained (the timer upcounter is cleared to 00h). only the nmi and reset signals used to release the software stop mode are valid, and all other functions stop. the statuses of the m pd78c17 and 78c18 output pins in the software stop mode are the same as for the halt mode, as shown in table 4-1. cautions 1. internal interrupts should be masked before executing the stop instruction to prevent errors due to an internal interrupt during the oscillation stabilization time at release of the software stop mode. 2. the timer1 match signal is used as the signal to start cpu operation to secure an oscillation stabilization period after the software stop mode has been released by setting the non- maskable interrupt request flag. thus, it is necessary to set a count value in timer reg which takes account of the oscillation stabilization time, and to set the timer mode register to the timer operating state, before executing the stop instruction. 4.4 software stop mode release (1) release by reset signal when the reset signal changes from the high to low level in the software stop mode, the software stop mode is released and clock oscillation starts as soon as the reset state is set. when the reset signal is driven high after oscillation has stabilized, the cpu starts program execution at address 0. when the reset signal changes from the high to low level, clock oscillation starts but it takes time for oscillation to stabilize. the reset signal low-level width must therefore be longer than the oscillation stabiliza- tion time. when the reset signal is input, the ram contents are retained but the contents of other registers are undefined. fig. 4-4 software stop mode release timing (reset input) cpu operation osc reset stop address 0 instruction execution if the software stop mode is released by the reset signal, program execution starts at address 0 as in the case of a normal power-on reset. the sb (standby) flag can be used to identify the program execution mode. the sb flag is set (1) when the v dd pin rises from the specified low level or below to the specified high level or above, and is reset (0) by executing a skip instruction. thus, by testing the sb flag using a skip instruction in the program executed after reset input, a set sb flag indicates a power-on start, and a reset sb flag indicates a start due to release of the software stop mode.
69 m pd78c17,78c18 cpu operation osc intfnmi stop interrupt execution wait (programmable) interrupt routine timer1 match signal (2) release by interrupt request flag when the non-maskable interrupt request flag is set in the software stop mode, the software stop mode is released and simultaneously clock oscillation starts. when clock oscillation starts, the timer upcounter starts counting up from 00h in accordance with the setting before execution of the stop instruction. cpu operation is started by a match signal (wait time taking account of the oscillation stabilization time) from the timer1 upcounter. in this case, the upcounter match signal does not set the interrupt request flag. the timer mode register of the timer after generation of the match signal is set to ffh and timer operation is stopped. after the elapse of the oscillation stabilization time, the program jumps to the interrupt address (0004h) irrespective of the interrupt enabled/disabled (ei/di) state and without executing the instruction following the stop instruction. fig. 4-5 software stop mode release timing 4.5 hardware stop mode when the stop signal changes from the high to low level, the hardware stop mode is set. in this mode all clocks stop. when the hardware stop mode is set, program execution stops and the internal ram contents just before stoppage are retained, and the stop signal used to release the hardware stop mode is valid. all other functions stop and the reset state is set. in the hardware stop mode, the m pd78c17 and 78c18 output pins become high-impedance.
70 m pd78c17,78c18 4.6 hardware stop mode release when the stop signal changes from the low to high level in the hardware stop mode, the hardware stop mode is released and simultaneously clock oscillation starts. after the elapse of the wait time (approximately 65 ms at 12 mhz) which takes account of the oscillation stabilization time, the cpu starts program execution at address 0 (see fig. 4-6 ). fig. 4-6 hardware stop mode release timing cpu operation instruction execution address 0 instruction execution stop osc wait approx. 65 ms/12 mhz the hardware stop mode is not released by a high-to-low transition of the reset signal. when the stop signal changes from low to high while the reset signal is low, the hardware stop mode is released and clock oscillation starts. if the reset signal returns from the low to high level, the cpu starts program execution at address 0 without waiting for the elapse of the oscillation stabilization time (see fig. 4-7 ). for also the case where the reset signal changes from high to low immediately after the hardware stop mode is released (the stop signal changes from low to high), the program is executed when the reset signal returns from low to high (see fig. 4-8 ). the oscillation stabilization time should therefore be taken into account when returning the reset signal to the high level. after reset signal input ram contents are retained, but the contents of other registers are undefined.
71 m pd78c17,78c18 fig. 4-7 hardware stop mode release timing fig. 4-8 hardware stop mode release timing in the case of a hardware stop mode release, as with a release of the software stop mode by means of the reset signal, it is possible to differentiate between a power-on start and a start due to release of the hardware stop mode by testing the sb flag using a skip instruction. 4.7 low supply voltage data retention mode the low supply voltage data retention mode can be set by decreasing the v dd supply voltage to 2.5 v after setting the software/hardware stop mode. ram contents can be retained with lower power consumption than in the software/hardware stop mode. caution the software/hardware stop mode should not be released while in the low supply voltage data retention mode. v dd must be raised to the normal operating voltage before the release is per- formed. cpu operation instruction execution address 0 instruction execution stop osc wait reset cpu operation instruction execution address 0 instruction execution stop osc wait reset
72 m pd78c17,78c18 5. reset operations when reset input becomes low, then system reset is activated to create the following status. o interrupt enable f/f is reset and interrupt is disabled. o all the interrupt mask registers are set (1) and interrupt is masked. o an interrupt request flag is reset (0) and pended interrupt is eliminated. o all psws are reset (0). o 0000h is loaded into the program counter (pc). o the mode a, mode b, mode c, and mode f registers are set to ffh and the bits (mm0, 1, and 2) of the mode control c and memory mapping registers are respectively reset (0), then all the ports (a, b, c, d, and f) become input port (high-impedance). o all the test flags but sb flag are reset (0). o a timer mode register is set to ffh, and timer f/f is reset. o the mode register (etmm, eom) of a timer/event counter is reset (0). o the serial mode high register (smh) of serial interface is reset (0), while the serial mode low register (sml) is set to 48h. o the a/d channel mode register of the a/d converter is reset (0). o wr, rd, ale signals become high-impedance. o the zc1, zc2 bits of the zero-cross mode register (zcm) are set (1). o data memory and the following register contents are undefined. o the internal timing generator is initialized. stack pointer (sp) expansion accumulator (ea, ea), accumulator (a, a) general register (b, c, d, e, h, l, b, c, d, e, h, l) output latch of each port timer reg0, 1 (tm0, tm1) timer/event counter reg0, 1 (etm0, etm1) rae bit of memory mapping register sb flag of test flag when reset input becomes high, the reset status is released. then, execution of the program is started from 0000h. the contents of various kinds of registers must be initialized or re-initialized in the program, if necessary.
73 m pd78c17,78c18 note nmi can also be described as fnmi. identifier description r v, a, b, c, d, e, h, l r1 eah, eal, b, c, d, e, h, l r2 a, b, c sr pa, pb, pc, pd, pf, mkh, mkl, anm, smh, sml, eom, etmm, tmm, mm, mcc, ma, mb, mc, mf, txb, tm0, tm1, zcm sr1 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm, rxb, cr0, cr1, cr2, cr3 sr2 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm sr3 etm0, etm1 sr4 ecmt, ecpt rp sp, b, d, h rp1 v, b, d, h, ea rp2 sp, b, d, h, ea rp3 b, d, h rpa b, d, h, d+, h+, dC, hC rpa1 b, d, h rpa2 b, d, h, d+, h+, dC, hC, d+byte, h+a, h+b, h+ea, h+byte rpa3 d, h, d++, h++, d+byte, h+a, h+b, h+ea, h+byte wa 8-bit immediate data word 16-bit immediate data byte 8-bit immediate data bit 3-bit immediate data f cy, hc, z irf nmi note , ft0, ft1, f1, f2, fe0, fe1, fein, fad, fsr, fst, er, ov, an4, an5, an6, an7, sb remarks 1. sr to sr4 (special register) 2. rp to rp3 (register pair) 4. f (flag) pa : port a etmm : timer/event pb : port b counter mode pc : port c eom : timer/event pd : port d counter output pf : port f mode ma : mode a anm : a/d channel mode mb : mode b cr0 : a/d conversion mc : mode c to result 0 to 3 mcc : mode control c cr3 mf : mode f txb : t x buffer mm : memory mapping rxb : r x buffer tm0 : timer reg0 smh : serial mode high tm1 : timer reg1 sml : serial mode low tmm : timer mode mkh : mask high etm0 : timer/event mkl : mask low counter reg0 zcm : zero cross mode etm1 : timer/event counter reg1 ecnt : timer/event counter upcounter ecpt : timer/event counter capture sp : stack pointer b:bc d:de h:hl v:va ea : extended accumulator b : (bc) d : (de) h : (hl) d+ : (de)+ h+ : (hl)+ dC : (de)C hC : (hl)C d++ : (de)++ h++ : (hl)++ d + byte : (de + byte) h + a : (hl + a) h + b : (hl + b) h + ea : (hl + ea) h + byte : (hl + byte) nmi : nmi input ft0 : intft0 ft1 : intft1 f1 : intf1 f2 : intf2 fe0 : intfe0 fe1 : intfe1 fein : intfein fad : intfad fsr : intfsr fst : intfst er : error ov : overflow an4 : analog input 4 to 7 to an7 sb : standby cy : carry hc : half carry z : zero 5. irf (interrupt flag) 6. instruction set 6.1 identifier/description of operand 3. rpa to rpa3 (rp addressing)
74 m pd78c17,78c18 6.2 symbol description of instruction code r 2 0 0 0 0 1 1 1 1 r 1 0 0 1 1 0 0 1 1 r 0 0 1 0 1 0 1 0 1 reg v a b c d e h l s 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 s 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 s 3 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 s 2 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 s 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 s 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 special-reg pa pb pc pd pf mkh mkl anm smh sml eom etmm tmm mm mcc ma mb mc mf txb rxb tm0 tm1 cr0 cr1 cr2 cr3 zcm rr1 sr u 0 0 1 special-reg etm0 etm1 v 0 0 1 special-reg ecnt ecpt p 2 0 0 0 0 1 p 1 0 0 1 1 0 p 0 0 1 0 1 0 reg-pair sp bc de hl ea q 2 0 0 0 0 1 q 1 0 0 1 1 0 q 0 0 1 0 1 0 reg-pair va bc de hl ea f 2 0 0 0 1 f 1 0 1 1 0 f 0 0 0 1 0 flag cy hc z sr3 sr4 rp rp1 f irf i 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 i 3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 i 2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 i 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 i 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 intf nmi ft0 ft1 f1 f2 fe0 fe1 fein fad fsr fst er ov an4 an5 an6 an7 sb t 2 0 0 0 0 1 1 1 1 t 1 0 0 1 1 0 0 1 1 t 0 0 1 0 1 0 1 0 1 reg eah eal b c d e h l rpa a 2 0 0 0 0 1 1 1 1 0 1 1 1 1 a 1 0 0 1 1 0 0 1 1 1 0 0 1 1 a 0 0 1 0 1 0 1 0 1 1 0 1 0 1 addressing (bc) (de) (hl) (de)+ (hl)+ (de)- (hl)- (de + byte) (hl + a) (hl + b) (hl + ea) (hl + byte) a 3 0 0 0 0 0 0 0 0 1 1 1 1 1 c 2 0 0 1 1 0 1 1 1 1 c 1 1 1 0 0 1 0 0 1 1 c 0 0 1 0 1 1 0 1 0 1 addressing (de) (hl) (de)++ (hl)++ (de + byte) (hl + a) (hl + b) (hl + ea) (hl + byte) c 3 0 0 0 0 1 1 1 1 1 rpa3 r r2 rpa rpa1 rpa2 sr sr1 sr2 rp rp2 rp3
75 m pd78c17,78c18 6.3 instruction execution time one state indicated in this section consists of three clock cycles. for example, one state takes 200 ns (1/15 ns 3) at 15-mhz operation, and when executing a 4-state instruction, the minimum execution time is 0.8 m s.
76 m pd78c17,78c18 note 1 mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition 8-bit data transfer instructions mov * * mvi r1, a a, r1 sr, a a, sr1 r, word word, r r, byte * sr2, byte mviw * wa, byte mvix rpa1, byte * staw * wa ldaw * wa stax * rpa2 ldax * rpa2 exx exa exh block dmov rp3, ea ea, rp3 00011t 2 t 1 t 0 00001t 2 t 1 t 0 01001101 01001100 01110000 01110000 01101r 2 r 1 r 0 01100100 01110001 010010a 1 a 0 01100011 00000001 a 3 0111a 2 a 1 a 0 a 3 0101a 2 a 1 a 0 00010001 00010000 01010000 00110001 101101p 1 p 0 101001p 1 p 0 11s 5 s 4 s 3 s 2 s 1 s 0 11s 5 s 4 s 3 s 2 s 1 s 0 01101r 2 r 1 r 0 01111r 2 r 1 r 0 data s 3 0000s 2 s 1 s 0 offset data offset offset data* 1 data* 1 low adrs low adrs data data high adrs high adrs r1 ? a a ? r1 sr ? a a ? sr1 r ? (word) (word) ? r 4 r ? byte sr2 ? byte (v. wa) ? byte (rpa1) ? byte (v. wa) ? a a ? (v. wa) (rpa2) ? a a ? (rpa2) b ? b', c ? c', d ? d' e ? e', h ? h', l ? l' v, a ? v', a', ea ? ea' (de) ? (hl) , c ? c ?1 end if borrow rp3 l ? eal, rp3 h ? eah eal ? rp3 l , eah ? rp3 h h, l ? h', l' 4 10 10 17 17 7 14 13 10 10 10 7/13* 3 7/13* 3 4 4 4 13 (c + 1) 4 4 note 2 ++ notes 1. instruction group 2. 16-bit data transfer instructions
77 m pd78c17,78c18 notes 1. instruction group 2. 8-bit operation instructions (register) note 1 mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition 16-bit data transfer instructions dmov steax sr3, ea ea, sr4 word word word word rpa3 word lded word lhld word lspd word ldeax rpa3 push rp1 pop * rp1 lxi table add adc 01001000 01110000 01001000 10110q 2 q 1 q 0 10100q 2 q 1 q 0 0p 2 p 1 p 0 0100 01001000 01100000 00011110 00101110 00111110 00001110 data* 2 low adrs low adrs high adrs high adrs sr3 ? ea (word) ? c, (word + 1) ? b (word) ? e, (word + 1) ? d (word) ? l, (word + 1) ? h (word) ? sp l , (word + 1) ? sp h (rpa3) ? eal, (rpa3 + 1) ? eah c ? (word), b ? (word + 1) e ? (word), d ? (word + 1) l ? (word), h ? (word + 1) sp l ? (word), sp h ? (word + 1) eal ? (rpa3), eah ? (rpa3 + 1) (sp ?1) ? rp1 h , (sp ?2) ? rp1 l rp2 ? word c ? (pc + 3 + a) 20 20 20 20 20 20 20 20 8 8 8 sbcd sded shld sspd lbcd rp2, word a, r r, a a, r r, a note 2 01110000 01001000 1101001u 0 1100000v 0 1001c 3 c 2 c 1 c 0 00011111 00101111 00111111 00001111 1000c 3 c 2 c 1 c 0 low byte 10101000 11000r 2 r 1 r 0 0100 1101 0101 data* 2 high byte 14 14 14/20 3 * 14/20 3 * 13 10 10 17 8 sp ? sp ?2 b ? (pc + 3 + a + 1) a ? a + r r ? r + a a ? a + r + cy r ? r + a + cy rp1 l ? (sp), rp1 h ? (sp + 1) sp ? sp + 2 ea ? sr4
78 m pd78c17,78c18 note instruction group note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition 8-bit operation instructions (register) addnc subnb a, r r, a a, r r, a a, r r, a a, r r, a ana a, r r, a ora a, r r, a xra a, r r, a gta lta nea 01100000 a ? a + r a ? a ?r r ? r ?a a ? a ?r ?cy r ? r ?a ?cy a ? a ?r r ? r ?a a ? a r 8 8 8 sub sbb a, r a, r r, a a, r r, a 10100r 2 r 1 r 0 0010 0011 1110 0110 8 a ?r r ?a r ? r + a r, a 1110 0110 1111 0111 1011 0011 10001r 2 r 1 r 0 0000 1001 0001 10010r 2 r 1 r 0 0001 10101 r 2 r 1 r 0 0010 1011 8 8 8 8 8 8 8 8 8 8 8 r ? r a a ? a r 8 8 8 8 8 r ? r a a ? a r r ? r a a ?r ?1 r ?a ?1 a ?r r ?a no carry no carry no borrow no borrow no zero no zero borrow borrow no borrow no borrow
79 m pd78c17,78c18 note instruction group note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition 8-bit operation instructions (memory) eqa addncx a, r r, a a, r a, r rpa rpa rpa rpa sbbx rpa rpa anax rpa rpa xrax rpa rpa ltax eqax 01100000 a ?r a r a r a ? a + (rpa) a ? a + (rpa) a ? a ?(rpa) a ? a ?(rpa) ?cy offa addx rpa rpa 11111r 2 r 1 r 0 0111 1100 1101 a ?(rpa) a (rpa) r ?a rpa 1100 1101 1101 1010 1110 1011 1001 1110 1111 8 8 8 8 11 a ? a ?(rpa) a ? a (rpa) a ? a (rpa) a ?(rpa) a ?(rpa) a (rpa) zero zero no carry no borrow zero no zero zero no borrow ona adcx subx subnbx orax gtax neax onax offax 01110000 11000a 2 a 1 a 0 1111 10001a 2 a 1 a 0 10010a 2 a 1 a 0 10101a 2 a 1 a 0 1011 a ? a + (rpa) + cy 11 11 11 11 11 11 11 11 11 11 11 11 11 11 no zero zero borrow no zero 8-bit operation instructions (register) a ?(rpa) ?1 a ? a (rpa) rpa rpa
80 m pd78c17,78c18 note instruction group note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition immediate data operation instructions aci * * adinc a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte * r, byte sr2, byte sui a, byte * r, byte sr2, byte sbi * suinb ani a, byte r, byte 01000110 01110100 0110 01010110 01110100 00100110 01110100 01100110 01110100 01110110 01110100 00110110 01110100 00000111 01110100 s 3 1000 s 2 s 1 s 0 01010r 2 r 1 r 0 data data data data a ? a + byte r ? r + byte sr2 ? sr2 + byte a ? a + byte + cy r ? r + byte + cy sr2 ? sr2 + byte + cy 7 a ? a + byte r ? r + byte sr2 ? sr2 + byte a ? a ?byte r ? r ?byte sr2 ? sr2 ?byte a ? a ?byte ?cy r ? r ?byte ?cy a ? a ?byte sr2 ? sr2 ?byte a ? a byte r ? r byte r ? r ?byte 20 11 20 7 11 20 11 20 7 7 adi a, byte r, byte sr2, byte a, byte r, byte sr2, byte 0110 0110 0110 0110 0110 data 01000r 2 r 1 r 0 data s 3 1010s 2 s 1 s 0 00100r 2 r 1 r 0 s 3 0100s 2 s 1 s 0 01100r 2 r 1 r 0 s 3 1100s 2 s 1 s 0 data 01110r 2 r 1 r 0 s 3 1110s 2 s 1 s 0 data 00110r 2 r 1 r 0 s 3 0110s 2 s 1 s 0 data data data data data 11 7 7 7 11 20 sr2 ? sr2 ?byte ?cy 11 20 no borrow no borrow no borrow no carry no carry no carry data * * 00001r 2 r 1 r 0 11
81 m pd78c17,78c18 note instruction group note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition immediate data operation instructions * * gti a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte * r, byte sr2, byte lti a, byte * r, byte sr2, byte nei * eqi 01100100 00010111 0110 00010110 01110100 00100111 01110100 00110111 01110100 01100111 01110100 01110111 01110100 00010r 2 r 1 r 0 data data data data a ? a byte r ? r byte sr2 ? sr2 byte a ? a byte r ? r byte sr2 ? sr2 byte a ?byte?1 r ?byte ?1 sr2 ?byte ?1 a ?byte r ?byte sr2 ?byte a ?byte sr2 ?byte r ?byte sr2 ?byte a ?byte 11 11 11 ori a, byte r, byte sr2, byte a, byte r, byte sr2, byte 0110 0110 0110 0110 0110 data data s 3 0010s 2 s 1 s 0 00101r 2 r 1 r 0 s 3 0101s 2 s 1 s 0 00111r 2 r 1 r 0 s 3 0111s 2 s 1 s 0 data 01101r 2 r 1 r 0 s 3 1101s 2 s 1 s 0 data 01111r 2 r 1 r 0 s 3 1111s 2 s 1 s 0 data data data 11 11 r ?byte 11 no zero data * ani sr2, byte xri zero 01110100 s 3 0001 s 2 s 1 s 0 00011r 2 r 1 r 0 s 3 0011 s 2 s 1 s 0 data 20 sr2 ? sr2 byte 7 20 7 20 7 14 7 14 7 14 7 14 zero zero no borrow no zero no zero borrow borrow borrow no borrow no borrow
82 m pd78c17,78c18 note instruction group note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition working register operation instructions offi * * addw a, byte r, byte sr2, byte a, byte r, byte sr2, byte wa wa wa sbbw wa wa wa oraw ltaw eqaw wa wa 01000111 01110100 0110 01010111 01110100 01110100 s 3 1001 s 2 s 1 s 0 01011r 2 r 1 r 0 data offset a byte r byte sr2 byte a byte r byte sr2 byte 7 a ? a + (v. wa) a ? a + (v. wa) + cy a ? a + (v. wa) a ? a ?(v. wa) a ? a ?(v. wa) a ? a (v. wa) a ? a (v. wa) a ?(v. wa) a ?(v. wa) a (v. wa) a ?(v. wa) 14 11 14 14 14 14 14 oni wa wa wa wa wa wa 0110 data 01001r 2 r 1 r 0 data s 3 1011s 2 s 1 s 0 1101 data 11 7 14 14 14 14 borrow no borrow no borrow no carry immediate data operation instructions adcw addncw subw subnbw anaw xraw gtaw neaw onaw 11000000 1010 1110 1111 1011 10001000 1001 10010000 10101000 1011 1110 1111 1100 14 14 14 a ? a (v. wa) 14 14 14 a ?(v. wa) ?1 a ? a ?(v. wa) ?cy no zero no zero no zero zero zero zero no zero zero no zero
83 m pd78c17,78c18 note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition working register operation instructions ltiw * * eqiw wa wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte dadd ea, r2 ea, rp3 ea, rp3 esub dsubnb dor ea, rp3 ea, rp3 01110100 00000101 0001 data a (v. wa) (v. wa) ? (v. wa) byte (v. wa) ? (v. wa) byte (v. wa) ?byte ?1 (v. wa) ?byte (v. wa) ?byte (v. wa) ?byte (v. wa) byte (v. wa) byte ea ? ea + r2 ea ? ea + rp3 +cy ea ? ea + rp3 ea ? ea ?r2 ea ? ea rp3 ea ? ea rp3 ea ? ea rp3 ea ? ea ?rp3 19 13 13 13 13 11 11 offaw ea, rp3 ea, r2 ea, rp3 ea, rp3 ea, rp3 ea, rp3 0111 11011000 offset 19 11 11 11 11 borrow no borrow no borrow no carry oniw offiw eadd dadc daddnc dsub dsbb dan dxr 1101 1010 1111 1011 1001 13 11 11 ea ? ea ?rp3 11 11 11 ea ? ea ?rp3 ?cy ea ? ea + rp3 zero zero zero no zero aniw * oriw gtiw neiw * * * * * 0010 0011 0100 0101 01110000 0100 0000 0100 010000r 1 r 0 110001p 1 p 0 011000r 1 r 0 111001p 1 p 0 100101p 1 p 0 100011p 1 p 0 0110 offset 14 13 no zero 16-bit operation instructions note instruction group
84 m pd78c17,78c18 note 1 mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition don mul ea, rp3 r2 inx wa rp ea dcrw daa clc 01110100 ea ?rp3 ?1 ea ?rp3 ea ?rp3 ea ?rp3 ea rp3 ea rp3 ea ? a r2 ea ? ea ? r2, r2 ? remainder r2 ? r2 + 1 (v. wa) ? (v. wa) + 1 ea ? ea + 1 r2 ? r2 ?1 (v. wa) ? (v. wa) ?1 cy ? 1 cy ? 0 a ? a + 1 decimal adjust accumulator 11 11 11 59 4 dgt r2 wa rp ea offset 11 16 borrow no borrow carry div inr inrw dcr dcx stc nega 32 16 rp ? rp ?1 ea ? ea ?1 rp ? rp + 1 zero zero no zero dlt dne deq doff * 00100000 001011r 1 r 0 00111010 11 11 16-bit operation instructions ea, rp3 ea, rp3 ea, rp3 ea, rp3 ea, rp3 r2 r2 01001000 010000r 1 r 0 00p 1 p 0 0010 10101000 010100r 1 r 0 00110000 00p 1 p 0 0011 10101001 01100001 01001000 101011p 1 p 0 1011 1110 1111 1100 1101 0011 offset 00101010 00101011 7 7 4 7 7 4 8 8 8 no zero carry borrow borrow note 2 addition/subtraction instructions note 3 * note 1. instruction group 2. multiply/divide instructions 3. other operation instructions
85 m pd78c17,78c18 note instruction group note mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition sll sllc r2 dsll ea ea ea jb jea calb 01001000 rotate left digit rotate right digit r2 m + 1 ? r2 m , r2 0 ? cy, cy ? r2 7 r2 m ?1 ? r2 m , r2 7 ? cy, cy ? r2 0 r2 m + 1 ? r2 m , r2 0 ? 0, cy ? r2 7 r2 m ?1 ? r2 m , r2 7 ? 0, cy ? r2 0 r2 m + 1 ? r2 m , r2 0 ? 0, cy ? r2 7 r2 m ?1 ? r2 m , r2 7 ? 0, cy ? r2 0 ea n + 1 ? ea n , ea 0 ? cy, cy ? ea 15 ea n ?1 ? ea n , ea 15 ? cy, cy ? ea 0 ea n ?1 ? ea n , ea 15 ? 0, cy ? ea 0 pc ? word pc h ? b, pc l ? c pc ? ea 8 rld word 17 carry slrc drll drlr jmp jr call calf pc ? pc + 1 + jdisp 1 pc ? pc + 2 + jdisp ea n + 1 ? ea n , ea 0 ? 0, cy ? ea 15 rrd rll rlr slr * 000001r 1 r 0 17 rotation/shift instructions r2 r2 r2 r2 r2 ea 01010100 00100001 11 0100111 01001000 01000000 00111000 low adrs 00101001 carry jump instructions call instructions dslr word jre word * * * word word 01001000 01111 jdisp 1 jdisp fa 00101000 low adrs 01r 1 r 0 1001 00r 1 r 0 001001r 1 r 0 00r 1 r 0 00r 1 r 0 10110100 0000 10100100 0000 high adrs high adrs 8 8 8 8 8 8 8 8 8 10 4 10 10 8 13 (sp ?1) ? (pc + 3) h , (sp ?2) ? (pc + 3) l (sp ?1) ? (pc + 2) h , (sp ?2) ? (pc + 2) l pc ? word, sp ? sp ?2 pc h ? b, pc l ? c, sp ? sp ?2 (sp ?1) ? (pc + 2) h , (sp ?2) ? (pc + 2) l pc 15 ?11 ? 00001, pc 10 ?0 ? fa, sp ? sp ?2 17 16
86 m pd78c17,78c18 *1. data is b2 if rpa2 = d + byte, h + byte. 2. data is b3 if rpa3 = d + byte, h + byte. 3. in the state item, a figure is in the right side of slash if rpa2 and rpa3 are d + byte, h + a, h + b, h + ea, h + byte. remarks the idle state when each instruction is skipped is different from the execution state as shown below. 1-byte instruction : 4 states 3-byte instruction (with *) : 10 states 2-byte instruction (with *) : 7 states 3-byte instruction : 11 states 2-byte instruction : 8 states 4-byte instruction : 14 states notes 1. instruction group 2. call instructions note 1 mnemonic operand b1 b2 b3 b4 instruction code state operation skip condition reti sk word f nop irf hlt 100 (sp ?1) ? (pc + 1) h , (sp ?2) ? (pc + 1) l pc l ? (sp), pc h ? (sp + 1) pc l ? (sp), pc h ? (sp + 1), sp ? sp + 2 pc l ? (sp), pc h ? (sp + 1) skip if (v. wa) bit = 1 skip if f = 1 skip if f = 0 skip if irf = 1, then reset irf skip if irf = 0 enable interrupt disable interrupt set halt mode 10 13 10 8 calt offset 16 12 uncondi- tional skip f = 1 skn skit sknit di stop set stop mode no operation (v. wa)bit = 1 softi ret rets bit * 00001f 2 f 1 f 0 16 10 bit, wa f irf 01001000 00000000 10101010 10111010 01001000 01001000 0001 10111011 00111011 4 4 4 note 2 cpu control instructions ei 01110010 10111000 1001 01100010 01011b 2 b 1 b 0 ta 010i 4 i 3 i 2 i 1 i 0 011i 4 i 3 i 2 i 1 i 0 pc l ? (128 + 2ta), pc h ? (129 + 2ta), sp ? sp ?2 (sp ?1) ? psw, (sp ?2) ? (pc + 1) h , (sp ?3) ? (pc + 1) l , pc ? 0060h, sp ? sp ?3 reset irf, if irf = 1 8 8 8 12 sp ? sp + 2 pc ? pc + n psw ? (sp + 2), sp ? sp + 3 f = 0 irf = 1 irf = 0 return instructions skip instructions
87 m pd78c17,78c18 7. list of mode registers h read/ name of mode registers function write ma mode a register w specifies bit-wise the input/output of the port a. mb mode b register w specifies bit-wise the input/output of the port b. mcc mode control w specifies bit-wise the port/control mode of the port c. c register mc mode c register w specifies bit-wise the input/output of the port c which is in port mode. mm memory mapping w specifies the port/expansion mode of port d and port f. register mf mode f register w specifies bit-wise the input/output of the port f which is in port mode. tmm timer mode register r/w specifies operating mode of timer. etmm timer/event counter w specifies the operating mode of timer/event counter. mode register eom timer/event counter r/w control the output level of co0 and co1. output mode register sml w serial mode register specifies the operating mode of serial interface. smh r/w mkl interrupt mask register r/w specifies the enable/disable of the interrupt request. mkh anm a/d channel mode r/w specifies the operating mode of a/d converter. register zcm zero-cross mode w specifies the operation of zero-cross detector circuit. register
88 m pd78c17,78c18 8. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit power supply voltage v dd C0.5 to +7.0 v av dd av ss to v dd + 0.5 v av ss C0.5 to +0.5 v input voltage v i C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v output current, low i ol per pin 4.0 ma total of all output pins 100 ma output current, high i oh per pin C2.0 ma total of all output pins C50 ma a/d converter reference v aref C0.5 to av dd + 0.3 v input voltage operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product with these rated values never exceeded. h h
89 m pd78c17,78c18 cautions 1. place the oscillator as close as possible to x1, x2 pins. 2. ensure that no other signal lines are routed through the area enclosed with dotted lines. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz 10 pf unmeasured pins output capacitance c o returned to 0 v 20 pf input-output capacitance c io 20 pf oscillator characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C 0.8 v av dd v dd , 3.4 v v aref av dd ) x1 x2 hcmos inverter resonator recommended circuit parameter test conditions min. max. unit ceramic oscillation frequency a/d converter not 4 15 mhz or (f xx ) used crystal resonator a/d converter used 5.8 15 mhz external x1 input frequency a/d converter not 4 15 mhz clock (f x ) used a/d converter used 5.8 15 mhz x1 rise time, 0 20 ns fall time (t r , t f ) x1 input high, low 20 250 ns level width (t ?h , t ?l ) x1 x2 c2 c1
90 m pd78c17,78c18 dc characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) parameter symbol test conditions min. typ. max. unit input voltage, low v il1 all except reset, stop, nmi, 0 0.8 v sck, int1, ti, an7 to an4 v il2 reset, stop, nmi, sck, int1, 0 0.2v dd v ti, an7 to an4 input voltage, v ih1 all except reset, stop, nmi, 2.2 v dd v high sck, int1, ti, an7 to an4, x1, x2 v ih2 reset, stop, nmi, sck, int1, 0.8v dd v dd v ti, an7 to an4, x1, x2 output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, v oh i oh = C1.0 ma v dd v high C 1.0 i oh = C100 m av dd v C 0.5 input current i i int1 note1 , ti (pc3) note2 ; 0 v v i v dd 200 m a input leakage i li all except int1, ti (pc3); 0 v v i v dd 10 m a current output leakage i lo 0 v v o v dd 10 m a current av dd power ai dd1 operating mode f xx = 15 mhz 0.5 1.3 ma supply current ai dd2 stop mode 10 20 m a v dd power i dd1 operating mode f xx = 15 mhz 16 30 ma supply current i dd2 halt mode f xx = 15 mhz 7 13 ma data retention v dddr hardware/software stop mode 2.5 v voltage data retention i dddr hardware/software note3 v dddr = 2.5 v 1 15 m a current stop mode v dddr = 5 v 10 % 10 50 m a pull-up resistor r l ports a, b, and c 3.5 v v dd 5.5 v, 17 27 75 k w v i = 0 v notes 1. if self-bias should be generated by zcm register. 2. if the control mode is set by mcc register, and self-bias should be generated by zcm register. 3. if self-bias is not generated.
91 m pd78c17,78c18 ac characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) read/write operation: parameter symbol test conditions min. max. unit x1 input cycle time t cyc 66 250 ns address setup time (to ale )t al f xx = 15 mhz, cl = 100 pf 30 ns address hold time (from ale )t la 35 ns rd delay time from address t ar 100 ns address float time from rd t afr c l = 100 pf 20 ns data input time from address t ad f xx = 15 mhz, c l = 100 pf 250 ns data input time from ale t ldr 135 ns data input time from rd t rd 120 ns rd delay time from ale t lr 15 ns data hold time (from rd - )t rdh c l = 100 pf 0 ns ale - delay time from rd - t rl f xx = 15 mhz, c l = 100 pf 80 ns rd low-level width t rr in data read 215 ns f xx = 15 mhz, c l = 100 pf in op code fetch 415 ns f xx = 15 mhz, c l = 100 pf ale high-level width t ll f xx = 15 mhz, c l = 100 pf 90 ns m1 setup time (to ale )t ml f xx = 15 mhz 30 ns m1 hold time (from ale )t lm 35 ns io/m setup time (to ale )t il 30 ns io/m hold time (from ale )t li 35 ns wr delay time from address t aw f xx = 15 mhz, c l = 100 pf 100 ns data output time from ale t ldw 180 ns data output time from wr t wd c l = 100 pf 100 ns wr delay time from ale t lw f xx = 15 mhz, c l = 100 pf 15 ns data setup time (to wr - )t dw 165 ns data hold time (from wr - )t wdh 60 ns ale - delay time from wr - t wl 80 ns wr low-level width t ww 215 ns
92 m pd78c17,78c18 serial operation : parameter symbol test conditions min. max. unit sck cycle time t cyk sck input note1 800 ns note2 400 ns sck output 1.6 m s sck low-level width t kkl sck input note1 335 ns note2 160 ns sck output 700 ns sck high-level width t kkh sck input note1 335 ns note2 160 ns sck output 700 ns r x d setup time (to sck - )t rxk note1 80 ns r x d hold time (from sck - )t krx note1 80 ns t x d delay time from sck t ktx note1 210 ns notes 1. if clock rate is 1 in asynchronous mode, synchronous mode, or i/o interface mode. 2. if clock rate is 16 or 64 in asynchronous mode. remark the numeric values in the table are those when f xx = 15 mhz, c l = 100 pf. zero-cross characteristics : parameter symbol test conditions min. max. unit zero-cross detection input v zx ac combination 1 1.8 vac p-p 60-hz sine wave zero-cross accuracy a zx 135 mv zero-cross detection input f zx 0.05 1 khz frequency other operation : parameter symbol test conditions min. max. unit ti high, low-level width t tih , t til 6t cyc ci high, low-level width t ci1h , t ci1l event count mode 6 t cyc t ci2h ,t ci2l pulse width test mode 48 t cyc nmi high, low-level width t nih , t nil 10 m s int1 high, low-level width t i1h , t i1l 36 t cyc int2 high, low-level width t i2h , t i2l 36 t cyc an7 to an4, low-level width t anh , t anl 36 t cyc reset high, low-level width t rsh , t rsl 10 m s
93 m pd78c17,78c18 a/d converter characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd , 3.4 v v aref av dd ) parameter symbol test conditions min. typ. max. unit resolution 8 bits absolute accuracy note 3.4 v v aref av dd , 66 ns t cyc 170 ns 0.8 % fsr 4.0 v v aref av dd , 66 ns t cyc 170 ns 0.6 % fsr t a = C10 to +70 c, 0.4 % fsr 4.0 v v aref av dd , 66 ns t cyc 170 ns conversion time t conv 66 ns t cyc 110 ns 576 t cyc 110 ns t cyc 170 ns 432 t cyc sampling time t samp 66 ns t cyc 110 ns 96 t cyc 110 ns t cyc 170 ns 72 t cyc analog input voltage v ian an7 to an0 (including unused pins) C0.3 v aref + 0.3 v analog input r an 50 m w impedance reference voltage v aref 3.4 av dd v v aref current i aref1 operating mode 1.5 3.0 ma i aref2 stop mode 0.7 1.5 ma av dd power supply ai dd1 operating mode f xx = 15 mhz 0.5 1.3 ma current ai dd2 stop mode 10 20 m a note quantization error ( 1/2 lsb) is not included. ac timing test point 2.2 v 0.8 v 2.2 v 0.8 v test points v dd ?1.0 v 0.45 v h
94 m pd78c17,78c18 parameter expression min./max. unit t al 2t C 100 min. ns t la t C 30 min. ns t ar 3t C 100 min. ns t ad 7t C 220 max. ns t ldr 5t C 200 max. ns t rd 4t C 150 max. ns t lr t C 50 min. ns t rl 2t C 50 min. ns t rr 4t C 50 (in data read) min. ns 7t C 50 (in op code fetch) t ll 2t C 40 min. ns t ml 2t C 100 min. ns t lm t C 30 min. ns t il 2t C 100 min. ns t li t C 30 min. ns t aw 3t C 100 min. ns t ldw t + 110 max. ns t lw t C 50 min. ns t dw 4t C 100 min. ns t wdh 2t C 70 min. ns t wl 2t C 50 min. ns t ww 4t C 50 min. ns t cyk 6t (sck input) note1 /12t (sck input) note2 min. ns 24t (sck output) t kkl 2.5t + 5 (sck input) note1 /5t + 5 (sck input) note2 min. ns 12t C 100 (sck output) t kkh 2.5t + 5 (sck input) note1 /5t + 5 (sck input) note2 min. ns 12t C 100 (sck output) notes 1. if clock rate is 16, 64 in asynchronous mode. 2. if clock rate is 1, in asynchronous mode, synchronous mode, or i/o interface mode. remarks 1. t = t cyc = 1/f xx 2. other items which are not listed in this table are not dependent on oscillator frequency (f xx ). t cyc -dependent ac characteristics expression
95 m pd78c17,78c18 mode1 (m1) x1 pf7 to pf0 pd7 to pd0 ale note1 mode0 (io/m) t cyc address (upper) address (lower) t rdh read data t ldr t ad t rl t rd t rr t afr t la t ll t ar t al t lr t ml t il t lm t li address (upper) t ldw t la t ll t al t wd t dw t wdh t wl t ww t lw t li t aw t il write data note2 x1 pf7 to pf0 pd7 to pd0 ale rd wr mode0 (io/m) note address (lower) timing waveform read operation notes 1. when mode1 pin is pulled up, m1 signal is output to mode1 pin in the 1st op code fetch cycle. 2. when mode0 pin is pulled up, io/m signal is output to mode0 pin in sr to sr2 register read cycle. write operation note when mode0 pin is pulled up, io/m signal is output to mode0 pin in sr to sr2 register write cycle.
96 m pd78c17,78c18 serial operation timer/event counter input timing timer input timing t cyk t kkl t kkh t rxk t krx t ktx sck t x d r x d ti t til t tih ci t ci1l t ci1h event counter mode ci t ci2l t ci2h pulse width test mode
97 m pd78c17,78c18 x1 t cyc t f h 0.8v dd 0.8 v t f t r t f l reset t rsl t rsh 0.8v dd 0.2v dd interrupt input timing external clock timing reset input timing nmi t nil t nih int1 int2 t i1h t i1l t i2l t i2h
98 m pd78c17,78c18 data memory stop mode low power supply voltage data retention (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention power v dddr 2.5 5.5 v supply voltage data retention power i dddr v dddr = 2.5 v 1 15 m a supply current v dddr = 5 v 10 % 10 50 m a v dd rise/fall time t rvd , t fvd 200 m s stop setup time t sstvd 12t + 0.5 m s (to v dd ) stop hold time t hvdst 12t + 0.5 m s (from v dd ) data retention timing 90 % stop v dd v dddr t rvd 10 % t fvd t sstvd t hvdst v ih2 v il2 h
99 m pd78c17,78c18 9. characteristic curves i dd1 , i dd2 vs v dd i dd1 , i dd2 vs f xx 30 25 20 15 10 5 0 0 4.5 5.0 5.5 (t a = 25 ?c, f xx = 15 mhz) i dd1 (typ.) i dd2 (typ.) power supply voltage v dd [v] v dd power supply current i dd1 , i dd2 [ma] (t a = 25 ?c, v dd = 5 v) oscillation frequency f xx [mhz] v dd power supply current i dd1 , i dd2 [ma] 30 20 10 0 0 5 10 15 i dd1 (typ.) i dd2 (typ.)
100 m pd78c17,78c18 i ol vs v ol i oh vs v oh 2.5 2.0 1.5 1.0 0.5 0 0 0.1 0.2 0.3 0.4 0.5 (t a = 25 ?c, v dd = 5 v) typ. output voltage low v ol [v] output current low i ol [ma] ?.5 ?.0 ?.5 0 0 0.1 0.2 0.3 0.4 0.5 (t a = 25 ?c, v dd = 5 v) power supply voltage ?output voltage high v dd ?v oh [v] output current high i oh [ma] typ.
101 m pd78c17,78c18 i dddr vs v dddr 10 8 6 4 2 0 0 23456 (t a = 25 ?c) typ. data retention power supply voltage v dddr [v] data retention power supply current i dddr [ m a]
102 m pd78c17,78c18 10. package drawings a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
103 m pd78c17,78c18 n a m f b 51 52 32 k l 64 pin plastic qfp (14 20) 64 1 20 19 33 p d c detail of lead end s q 55 g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009
104 m pd78c17,78c18 64 pin plastic quip (unit: mm) h i m c p a 64 132 33 m n j k s w x p64gq-100-36 item millimeters inches a c h i j k m n p s w 1.27 (t.p.) 0.25 16.5 0.100 (t.p.) 0.050 (t.p.) 0.010 0.157 1.634 note x 4.0 0.750 each lead centerline is located within 0.25 mm (0.010 inch) of its true position (t.p.) at maxi- mum material condition. 0.142 0.043 0.020 24.13 0.950 0.010 0.25 2.54 (t.p.) +0.004 ?.005 +0.011 ?.006 +0.012 ?.008 +0.004 ?.005 41.5 +0.3 ?.2 0.50 +0.10 1.1 +0.25 ?.15 +0.10 ?.05 +0.3 3.6 +0.1 +1.05 19.05 +1.05 0.650 +0.004 ?.003 +0.013 ?.012 +0.042 +0.042
105 m pd78c17,78c18 package peak temperature: 215 c, time: within 40 s (at 200 c or higher), count: twice or less (1) perform the second reflow when the device temperature has come down to the room temperature from the heating by the first reflow. (2) do not wash the soldered portion with flux following the first reflow. package peak temperature: 235 c, time: within 30 s (at 210 c or higher), count: twice or less (1) perform the second reflow when the device temperature has come down to the room temperature from the heating by the first reflow. (2) do not wash the soldered portion with flux following the first reflow. 11. recommended soldering conditions this m pd78c17 and 78c18 should be soldered and mounted under the following recommended conditions. for details of the conditions, refer to the document "surface device mounting technology manual" (iei- 1207). for soldering methods and conditions other than those recommended below, contact an nec sales repre- sentative. table 11-1 surface mounting type soldering conditions m pd78c17gf-3be: 64-pin plastic qfp (14 20 mm) m pd78c18gf- -3be: 64-pin plastic qfp (14 20 mm) recommended soldering method soldering conditions condition symbol infrared ray reflow ir35-00-2 vsp vp15-00-2 wave soldering ws60-00-1 partial heating CC caution do not use several soldering methods in combination (except partial heating). table 11-2 through-hole type soldering condition m pd78c17cw: 64-pin plastic shrink dip (750 mils) m pd78c18cw- : 64-pin plastic shrink dip (750 mils) m pd78c17gq-36: 64-pin plastic quip m pd78c18gq- -36: 64-pin plastic quip soldering method soldering conditions wave soldering (pin only) solder bath temperature: 260 c or lower, time: within 10 s partial heating pin temperature: 300 c or lower, time: within 3 s (per pin) caution wave soldering must be applied to pins only, and care must be taken to prevent solder from coming into direct with the package body. h solder bath temperature: 260 c or lower, time: within 10 s, count: once, preheating temperature: 120 c max. (package surface temperature) pin temperature: 300 c or lower, time: within 3 s (per pin row)
106 m pd78c17,78c18 12. differences among m pd78c18, m pd78c14, and m pd78c12a m pd78c14 16 k 8 no on-chip pull-up resistor ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic quip ? 64-pin plastic quip (straight) part number item internal rom internal ram port a to port c package m pd78c18 32 k 8 1 k 8 on-chip pull-up resistor selectable bit-wise by mask option ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic quip m pd78c12a 8 k 8 on-chip pull-up resistor selectable bit-wise by mask option ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic quip ? 64-pin plastic quip (straight) ? 68-pin plastic qfj 256 8
107 m pd78c17,78c18 appendix development tools the following development tools are available to develop a system which uses the m pd78c17 or 78c18. language processor h ordering code (product name) m s5a13ra87 m s5a10ra87 m s7b13ra87 m s7b10ra87 host machine pc-9800 series ibm pc/at tm this is a program which converts a program written in mnemonic to an object code for which microcontroller execution is possible. besides, it contains a function to automatically create a symbol table, and optimize a branch instruction. 87ad series relocatable assembler (ra87) pg-1500 pa-78cp14cw/ gf/gq pa-78cp14cw pa-78cp14gf pa-78cp14gq pg-1500 controller with a provided board and an optional programmer adapter connected, this prom programmer can manipulate from a stand-alone or host machine to perform programming on single-chip microcontroller which incorporates prom. it is also capable of programming a typical prom ranging from 256 k to 4 mbits. prom programmer adapter for the m pd78cp18. used by connecting to pg-1500. for the m pd78cp18cw for the m pd78cp18gf-3be for the m pd78cp18gq-36 connected pg-1500 to a host machine by using serial and parallel interfaces, to control the pg- 1500 on a host machine. hardware note ver. 5.00/5.00a are provided with the task swap function, but it cannot be used with this software. remark operation of assemblers and the pg-1500 controller are guaranteed only on the host machines and operating systems shown above. ordering code (product name) m s5a13pg1500 m s5a10pg1500 m s7b10pg1500 host machine pc-9800 series ibm pc/at os ms-dos ver. 2.11 to ver. 5.00a note pc dos (ver. 3.1) software prom write tools os ms-dos tm ver. 2.11 to ver. 5.00a note pc dos tm (ver. 3.1) supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc
108 m pd78c17,78c18 debugging tools an in-circuit emulator (ie-78c11-m) is available as a program debugging tool for the m pd78c17 and 78c18. the following table shows its system configuration. the ie-78c11-m is an in-circuit emulator which works with 87ad series. it can be connected to a host machine to perform efficient debugging. connects the ie-78c11-m to host machine by using the rs-232c, then controls the ie-78c11-m on host machine. ie-78c11-m ie-78c11-m control program (ie controller) ordering code (product name) m s5a13ie78c11 m s5a10ie78c11 m s7b10ie78c11 supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc host machine pc-9800 series ibm pc/at os ms-dos ver. 2.11 to ver. 3.30d pc dos (ver. 3.1) software remark operation of the ie controller is guaranteed only on the host machine and operating systems quoted above. hardware
109 m pd78c17,78c18 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function. ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation.
m pd78c17,78c18 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 license not needed: m pd78c17cw, 78c17gf-3be, and 78c17gq-36 the customer must judge the need for license: m pd78c18cw- , 78c18gf- -3be, and 78c18gq- -36 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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